Method fabricating an integrated circuit

Details Method fabricating an integrated circuit Method fabricating an integrated circuit

1993-12-22

1996-08-06

Dang, Trung

Fishing, trapping, and vermin destroying

437 69, 437 70, 437186, 437 40, H01L 2170, H01L 2700

Patent

active

055433430

ABSTRACT:
A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.

REFERENCES:
patent: 4026740 (1977-05-01), Owen, III
patent: 4160987 (1979-07-01), Dennard et al.
patent: 4266985 (1981-05-01), Ito et al.
patent: 4407696 (1983-10-01), Han et al.
patent: 4508757 (1985-04-01), Fabricius et al.
patent: 4551910 (1985-11-01), Patterson
patent: 4553314 (1985-11-01), Chan et al.
patent: 5151381 (1992-09-01), Liu et al.
patent: 5192707 (1993-03-01), Hodges et al.
patent: 5210056 (1993-05-01), Pong et al.
patent: 5258333 (1993-11-01), Shappir et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5264724 (1993-11-01), Brown et al.
patent: 5296411 (1993-04-01), Gardner et al.
patent: 5310692 (1994-05-01), Chan et al.
"An Integrated Isolation/Gate Process for Sub-Quarter Micron Technologies", AT&T, 1993, Symposium on VLSI Technology, pp. 141-142.
"VIB-1 Integration of Poly Buffered LOCOS and Gate . . . ", AT&T, IEEE Transactions on Electron Devices, V. 38, No. 12, Dec. 1991, p. 2721.
"Residual Stress, Chemical Etch Rate, Refractive Index . . . ", Irene et al., J. Electrochem Soc., Feb. 1980, pp. 396-399.
"Dry Pressure Local Oxidation of Silicon for IC Isolation", Marshall, et al., J. Electrochem. Society, V. 122, No. 10, Oct. 1975, pp. 2411-2412.
"Low Temperature Thermal Oxidation of Silicon . . . ", Zeto, et al., J. Electrochemical Society, V. 122, No. 10, Oct. 1975, pp. 1409-1410.
"Twin-White-Ribbon Effect and Pit Formation Mechanism in PBLOCOS", Lin, et al., J. Electrochem Soc., V. 138, No. 7, Jul. 1991, pp. 2145-2149.

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