Method DRAM polycide rowline formation

Details Method DRAM polycide rowline formation Method DRAM polycide rowline formation

1993-05-26

1995-06-20

Thomas, Tom

Fishing, trapping, and vermin destroying

437 52, 437174, 437233, 437248, H01L 218239

Patent

active

054253926

ABSTRACT:
The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the gate oxide layer in situ by exposing the silicon substrate to a first gas comprising at least one of silane, disilane, and dichlorosilane, and radiant energy at a temperature substantially within the range of 500.degree. C. to 1250.degree. C. for at least 10 seconds. The polysilicon substrate can be doped with a material such as phosphorus, arsenic and boron for example, by exposing the polysilicon to a second gas under the stated conditions. A conductive layer comprising at least one of tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) can be formed superjacent the polysilicon by exposing the polysilicon to a third gas comprising at least one of WF.sub.6, TMAT and TiCl.sub.4.

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Ghandhi, "VLSI Fabrication Principles," John Wiley & Sons, 1983, pp. 591-592.
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Mayo, "Photodeposition: Enhancement of Deposition by Heat and Light" Solid State Technology. 1986 pp. 141-1986.

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