Data processing: measuring – calibrating – or testing – Measurement system – Remote supervisory monitoring
Reexamination Certificate
2001-12-21
2004-11-09
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Remote supervisory monitoring
C709S203000, C307S042000, C370S386000
Reexamination Certificate
active
06816818
ABSTRACT:
The invention is based on a priority application DE 10064928.9, which is incorporated by reference herein.
FIELD OF THE INVENTION
The present invention relates to the field of telecommunications and computer technology and more particularly to a method of synchronizing at least one receiver module, a synchronizable receiver module therefor, and a clock generator module therefor.
BACKGROUND OF THE INVENTION
In the telecommunications and computer technology sectors, the assemblies required for the operation of a device often cannot be arranged on one electronic board but must be distributed between a plurality of separate modules on one or more respective boards. In particular in telecommunications systems, redundant modules are also used as a safeguard against failure. For the modules to operate synchronously, the receiver modules receive a central clock signal which in the simplest case is only one clock pulse.
A central clock signal of this kind is generated for example by a central clock generator module and transmitted to the receiver modules. A clock channel of a bus to which the receiver modules are connected is provided for example for the transmission. The receiver modules then operate either directly with the clock signal tapped from the bus or for example synchronize their own local clock generator, provided on the respective receiver module, with the central clock signal.
In a consequently redundant system, a receiver module is however supplied not only with one clock signal but with at least one second clock signal, in which case the connected receiver modules select one of the clock signals as master synchronization signal for their synchronization and the other clock signal(s) serve as slave synchronization signals which are selected as clock signal(s) upon the failure of the master synchronization signal. Ideally all the clock signals are synchronous, the slave clock signals being synchronized for example with the master clock signals so that the receiver modules to be synchronized in principle can select any one of the clock signals as their respective master synchronization signal without any phase difference.
However, in high-precision network devices of telecommunications networks operating at a high clock frequency, for example in so-called cross-connects in SDH transmission technology (SDH=synchronous digital hierarchy), even very small phase shifts between the individual clock signals have a disturbing influence on the precision of the network device. The modules of a network device, which for example are I/O assemblies (I/O=input/output) or switching matrices, then no longer operate sufficiently in synchronism and messages passing through the modules of the network device are subject for example to data overtaking or overlaps.
The same problems arise even if, for reasons of redundancy, network devices in a telecommunications network are synchronized with more than one clock signal.
SUMMARY OF THE INVENTION
Therefore the object of the invention is to provide a method and device for a precise synchronization of at least one receiver module, in particular a receiver module in a telecommunications network or in a network device of a telecommunications network.
This object is achieved by a method of synchronizing at least one receiver module, in particular a receiver module in a telecommunications network or in a network device of a telecommunications network, which has the following steps: A first clock signal and a second clock signal are sent to the at least one receiver module. In addition, at least one item of master-slave-status information about the at least one first clock signal and/or the second clock signal is sent to the at least one receiver module. Based on the item of master-slave-status information, the at least one receiver module selects the first clock signal or the second clock signal as master synchronization signal for its synchronization.
The invention is based on the principle that the respective receiver module, which is sent at least one first clock signal and a second clock signal, and selects the at least one first clock signal or the second clock signal as master synchronization signal for its synchronization, is sent, in addition to the clock signals, an item of master-slave-status information about the clock signals, on the basis of which information the receiver module can determine which of the clock signals is currently the master clock signal and which clock signal is the slave clock signal. The receiver module then selects the clock signal identified as master synchronization signal for its synchronization and thus synchronizes itself with the clock signal operating with a higher degree of precision.
The invention can be used advantageously in any system with redundant clock distribution. The system can consist of one single device or for example a communications network. In a particularly preferred embodiment the invention is used in a transmission network, in particular a transmission network with a synchronous digital hierarchy (SDH) or in a network device of the transmission network, for example in a cross-connect of a SDH transmission network, a SONET network device (SONET=synchronous optical network) or a PDH network device (PDH=plesiosynchronous digital hierarchy). The receiver modules consist for example of input/output modules or switching matrix modules, which in all events require precise synchronization for smooth mutual cooperation.
Further advantageous developments of the invention are described in the dependent claims and in the description.
The master-slave-status information can in principle be sent to the receiver module(s) in addition to the respective clock signals as separate control information, for example on a separate data line.
The master-slave-status information can also be contained in the respective clock signals, at least partially so-to-speak as “in-band-identifier”. Here different variants are conceivable. For example a master/slave identifier, for example in the form of one bit, could be attached to the clock signals. Moreover, only that clock signal to which a master identifier is added could be characterised as master synchronization signal, while clock signals with no identifier are automatically regarded as slave clock signals. Additionally, only the slave clock signals, not however the master clock signal, could be identified.
Advantageously, one of the clock signals is defined as a preferred master synchronization signal. If it is then undetectable, on the basis of the item of master-slave-status information, as to which of the clock signals is to be selected as the master synchronization signal, for example because the master-slave-status information is not sent or is sent faultily to the respective receiver module or the master-slave-status information identifies more than one clock signal as master synchronization signal, the receiver module selects the clock signal defined as preferred master synchronization signal. Faults relating to the. master-slave-status information thus hardly affect the precision of the synchronization.
The clock signals are preferably generated by one or more clock generator module(s). These can for example each have their own clock generator, for example comprising an oscillator, and/or can regenerate a clock received from the exterior and distribute this among the receiver modules which they are assigned. The latter applies for example to SDH cross-connects, in the case of which input/output modules receive external clock signals at so-called I/O ports (I/O=input/output) respectively assigned to transmission paths. The clock generator modules preferably select the I/O port with the best clock quality as clock source and from the clock information thereof generate the redundant clock signals intended for the receiver modules.
The clock signals distributed by the clock generator modules are preferably synchronous with one another. For this purpose at least one first (master) clock generator module, which for example normal
Beisel Werner
Höhn Jürgen
Wolf Michael Joachim
Alcatel
Barlow John
Bhat Aditya
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