Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-05-06
2008-05-06
Ho, Hoai V. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185240, C365S185290
Reexamination Certificate
active
11335318
ABSTRACT:
The present invention is a method, circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array or array segment. According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more NVM cells within an array segment may be at least partially based on one or more erase pulse parameters associated with the given array segment.
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Eisen Shai
Shappir Assaf
EMPK & Shiloh, LLP
Ho Hoai V.
Saifun Semiconductors Ltd.
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