Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-09-28
2001-06-19
Riley, Shawn (Department: 2838)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C307S029000, C307S086000, C326S083000
Reexamination Certificate
active
06249177
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for providing a supply voltage to low-voltage devices generally and, more particularly, to a method and/or architecture for providing a supply voltage while reducing gate oxide stress in low-voltage devices.
BACKGROUND OF THE INVENTION
Conventional approaches for regulated devices implement independent regulators for analog portions (i.e., phase lock loops (PLLs)) and digital portions(i.e., logic core) of a circuit. With independent regulators, switching in the core does not affect the PLL devices. However, providing separate reference voltages requires additional overhead.
It is desirable to provide a circuit to prevent gate oxide breakdown of regulated, thin-oxide devices in a PLL when another device, implemented on the same integrated circuit (IC), is operated when the PLL is powered down.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit, a second circuit, and a switch. The first circuit may be configured to receive a first supply voltage and may be coupled to a first ground. The second circuit may be configured to receive a second supply voltage and may be coupled to a second ground. The second circuit may be disabled in response to a control signal. The first and second supply voltages may be controlled by a common reference voltage. The switch may be coupled between the first and second circuits and may be configured to connect the first and second circuits when the second circuit is disabled.
The objects, features and advantages of the present invention include providing a method and/or architecture for reducing gate oxide stress in low-voltage devices that may (i) improve reliability, particularly with low-voltage, thin-oxide, regulated devices in circuits such as PLLs; (ii) provide an increased margin to avoid excess gate-oxide stress; (iii) implement a simple design without a need for managing the design of an additional regulator; and/or (iv) provide an implementation that saves die size compared with implementing an additional regulator.
REFERENCES:
patent: 6127848 (2000-10-01), Wert et al.
Saripella Satish C.
Savage Derrick J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Riley Shawn
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