Method/architecture for a low gain PLL with wide frequency...

Details Method/architecture for a low gain PLL with wide frequency... Method/architecture for a low gain PLL with wide frequency...

2002-02-26

2004-01-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06680632

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing a phase lock loop (PLL) generally and, more particularly, to a method and/or architecture for implementing a wide frequency range PLL without suffering from noise sensitivities inherent in typical high gain PLL systems.
BACKGROUND OF THE INVENTION
PLLs are often implemented as clock multipliers. For example, an input clock frequency of 20 Mhz can be multiplied by a PLL to yield an output frequency of 1000 Mhz. Ideally, the clock multiplication would result in an output clock that is in perfect phase alignment with the input clock.
Referring to
FIG. 1
, a conventional PLL architecture
10
is shown. The PLL
10
includes a phase frequency detector (PFD)/charge pump
14
, a filter
16
, a voltage controlled oscillator (VCO)
18
, a divider
20
, and a divider
22
. The PFD section of the circuit
14
presents charge pump section signals in response to the frequency and phase of the reference signal REF relative to the feedback clock FB. The charge pump section of the circuit
14
pumps up or down in response to the frequency and presents a signal to the filter
16
. The filter
16
integrates the filter signal into a voltage. The VCO
18
converts the voltage signal into the clock signal CLK_OUT. The divider
20
divides down the higher speed frequency (i.e., 1000 MHZ) of the signal CLK_OUT for comparison by the PFD/charge pump
14
at 10 MHZ. A divider
22
divides the input frequency (i.e., 20 MHZ) of the signal CLK_IN before being presented to the PFD/charge pump
14
as the reference frequency (i.e, 10 MHZ) REF.
Referring to
FIG. 2
, a timing diagram
50
illustrating PLL lock time versus frequency is shown. The lock time of a PLL is greater as the operating frequency of the PLL is increased.
There are several conventional approaches for obtaining wide frequency range in a PLL. In one approach, the VCO must inherently have large gain (MHZ/V) to cover the operating frequency range over process variations. Such high gains VCOs are inherently sensitive to noise. For example, low frequency input noise on filter nodes is multiplied by the gain resulting in unwanted frequencies (jitter). Jitter is undesirable in PLLs, in particular to PLLs in SONET applications.
Another conventional approach for obtaining a wide frequency range in a VCO is described in “A 6-Ghz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistor—IEEE, Journal of solid-state Circuits, vol. SC-27, pp. 1752-1762, December 1992”. The article shows fine and coarse control on the VCO. The PLL operates in either a high gain (MHZ/V) or a low gain mode. The high gain mode will typically result in faster lock time and wide frequency range, but at the expense of increasing jitter. Once such a system is close to locking, the system switches to the lower VCO gain, therefore achieving fast lock time without sacrificing jitter.
However, such an approach requires a logic decision to inform the system when to switch from coarse control mode to fine control mode. Such logic complicates the PLL design. Also, once the PLL is in fine mode, the coarse mode has to be disabled. Disabling the coarse mode without losing PLL lock or generating noise can be difficult to implement. The range of the VCO in the fine mode must be wide enough to keep the PLL locked over operating temperature without activating the coarse mode.
It would be desirable to implement a noise resistant PLL that has a wide frequency range, but does not suffer from using additional logic and/or other adaptive systems to control the PLL during startup.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.
The objects, features and advantages of the present invention include providing a method and/or architecture for a wide frequency range PLL that may be implemented (i) without suffering from the noise sensitivities inherent in the high gain PLL system (ii) with an op-amp in the high gain path, (iii) with an op-amp and low pass filter in the high gain loop, (iv) with the integration of the main filter with a high gain path filter (e.g., without separate filters), (v) via high and low gain architectures which are always on (e.g., instead of being switched in/out), (vi) via high and low gain architectures which are self-adaptive (e.g., without decision logic), (vii) with a reference to set up the desired filter node, (viii) with a filter node to drive the buffer in the high gain path and/or (ix) with an internal filter node to drive the buffer in the high gain path.


REFERENCES:
patent: 5854575 (1998-12-01), Fiedler et al.
patent: 5949289 (1999-09-01), Smith et al.
patent: 6462623 (2002-10-01), Horan et al.
“A 6-GHz Integrated Phase-Locked Loop Using A1GaAs/GaAs Heterojunction Bipolar Transistors”, By Aaron W. Buchwald et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1752-1762.

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