Method, architecture and circuit for half-rate clock and/or data

Details Method, architecture and circuit for half-rate clock and/or data Method, architecture and circuit for half-rate clock and/or data

1999-04-01

2000-06-13

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 11, 331 12, 331 14, 331 17, 331DIG2, 375376, H03L 7087, H03L 7095, H03L 7099

Patent

active

060754168

ABSTRACT:
A circuit comprising an oscillator, a multiplexer, a half rate clock circuit and a full rate clock circuit. The oscillator may be configured to generate a first clock signal and a second clock signal in response to a control signal. The multiplexer may be configured to generate the control signal in response to (i) a half-rate clock signal and (ii) a full rate clock signal. The half rate clock circuit may be configured to generate the half rate clock signal in response to the first and second clock signals. The full rate clock circuit may be configured to generate the full rate clock in response to (i) one of the first and second clock signals and (ii) a reference clock.

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