Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Patent
1993-11-30
2000-01-18
An, Meng-Al T.
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
708500, 708560, G06F 1500
Patent
active
060165383
ABSTRACT:
This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input. The arithmetic logic unit (230) receives the single data word at a first input (241) and the rotated single data word at a second input (241). The mask supplies the third input (243). The arithmetic logic unit (230) then forms the combination (A&C)+(B&C), which is field addition of A and B as masked by C. With proper selection of the mask and the rotate amount, the three input arithmetic logic unit (230) forms the shift, mask and addition in a single cycle. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
REFERENCES:
patent: 4467444 (1984-08-01), Harmon, Jr. et al.
patent: 4592005 (1986-05-01), Kregness
patent: 4692888 (1987-09-01), New
patent: 4785393 (1988-11-01), Chu et al.
patent: 4817028 (1989-03-01), Masson et al.
patent: 4821225 (1989-04-01), Ando et al.
patent: 4872131 (1989-10-01), Kubota et al.
patent: 4901270 (1990-02-01), Galbi et al.
patent: 4924422 (1990-05-01), Vassiliadis et al.
patent: 4953115 (1990-08-01), Kanoh
patent: 4982352 (1991-01-01), Taylor et al.
patent: 5103419 (1992-04-01), Toyokura et al.
patent: 5185714 (1993-02-01), Nakayama
patent: 5197140 (1993-03-01), Balmer
patent: 5212777 (1993-05-01), Goye et al.
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
Microprocessor Report Slater Michael, "ITT Ships Programmable Video Processor," vol. 5, No. 20, Oct. 30, 1991, pp. 1, 6-7, 13.
Guttag Karl M.
Read Christopher J.
An Meng-Al T.
Davis Jr. Walter D.
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
LandOfFree
Method, apparatus and system forming the sum of data in plural e does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, apparatus and system forming the sum of data in plural e, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, apparatus and system forming the sum of data in plural e will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-570374