Method, apparatus and system for optimizing packet...

Details Method, apparatus and system for optimizing packet... Method, apparatus and system for optimizing packet...

2007-09-17

2010-06-29

Pezzlo, John (Department: 2465)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S252000, C370S412000

Reexamination Certificate

active

07746856

ABSTRACT:
An apparatus and system provide an optimizing content processing throughput for systems on chips (“SoCs”). A Packet Processing Memory Controller Cache (“PPMCC”) on an SoC according to an embodiment of the present invention may enable the SoC to store content packets within the SoC, thus eliminating the need to write to and read from external memory. Additionally, by utilizing Quality of Service (“QoS”) tags for the content packets received by the SoC, PPMCC may enforce a unique caching policy which optimizing content processing. Finally, an Address Translation Lookup Table (“ATLT”) on the SoC enables packet processing controllers on the SoC to route packets directly amongst themselves by identifying the source and destination of each content packet.

REFERENCES:
patent: 2002/0091916 (2002-07-01), Dowling
Ram Huggahalli, et al., “Direct Cache Access for High Bandwidth Network I/O”, Proceedings of the 32nd International Symposium on Computer Architecture (ISCA'05), 2005 IEEE (10 pages).

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