Method, apparatus, and system for high speed data transfer...

Details Method, apparatus, and system for high speed data transfer... Method, apparatus, and system for high speed data transfer...

2000-03-31

2003-09-16

Le, Thong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S193000

Reexamination Certificate

active

06621760

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the field of data transfer technology. More specifically, the present invention relates to a method, apparatus, and system for high speed data transfer using source synchronous data strobe.
BACKGROUND OF THE INVENTION
Currently, graphics controllers/accelerators such as the Intel 740 supports local memory interface from 66.67 MHz to 100 MHz. A typical graphics controller such as the Intel 740 has its own local memory that can be SDRAM or Dual Data Rate SDRAM. DDR SDRAM specifies data transfers at 2× the maximum transfer rate. For a 100 MHz DDR SDRAM, control would be transferred at 1× speed (e.g., once every 100 MHz clock) whereas data would be transferred at 2× speed (twice every 100 MHz clock). As DRAM vendors move their silicon to next generation processes (e.g., less than or equal to 0.25 microseconds), the capability to produce higher frequency SDRAM parts will increase up to a maximum of 150 MHz at the system level. The loading on control signals is higher than that on data lines which restricts going beyond 150 MHz. DDR takes advantage of the lighter data load and increases the data transfer rate. As a result, graphics controllers/accelerators need to be able to accommodate high speed data transfer at higher frequencies than 100 MHz.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.


REFERENCES:
patent: 6128248 (2000-10-01), Idei et al.
patent: 6275086 (2001-08-01), Douchi et al.
patent: 6374360 (2002-04-01), Keeth et al.
patent: 6397312 (2002-05-01), Nakano et al.
patent: 2002/0091958 (2002-07-01), Schoenfeld et al.

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