Method, apparatus and program for creating a power pin model...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

Reexamination Certificate

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Reexamination Certificate

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07962320

ABSTRACT:
A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI. Here, the size of each divided cell is determined to be electrically sufficiently smaller than a wavelength corresponding to an upper limit analysis frequency derived from power supply circuit network wire information, transistor structure information, and analysis frequency information.

REFERENCES:
patent: 6577994 (2003-06-01), Tsukuda
patent: 2002/0011885 (2002-01-01), Ogawa et al.
patent: 11-87512 (1999-03-01), None
patent: 2001-222573 (2001-08-01), None
patent: 2001-256271 (2001-09-01), None
patent: 2002-222230 (2002-08-01), None
patent: 2002-304434 (2002-10-01), None
patent: 2004-234618 (2004-08-01), None

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