Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1996-10-10
2001-06-19
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S524000
Reexamination Certificate
active
06249798
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a transfer and translation of information between an integer processing unit and a floating point processing unit. More particularly, the present invention relates to direct transfer between and translation of data stored in a memory format in integer registers of the integer processing unit and data stored in a floating point format in floating point registers of the floating point processing unit.
The use of integer and floating point processing units within or in conjunction with a microprocessor is well known in the data processing art. The integer processing unit provides the basic arithmetic and logical operations for the processor when the information is in integer format and the floating point processing unit provides the basic arithmetic and logical operations for the processor in floating point format when floating point operations are to be performed. Typically, there are two sets of registers including a first set of integer registers for the integer unit and a second set of floating point registers for the floating point unit. Further, the bit length of the two register sets may differ in order to accommodate the higher precision capability of the floating point unit. For example, the integer registers may each be 32 bits in length, while the floating point registers may each be 64 bits or greater.
In current microprocessor technology, a typical integer unit includes a number of integer registers which store information and one or more integer execution units which operate on the stored information based on instructions conveyed to the execution unit(s). The integer registers for the integer unit are sometimes collectively referred to as a file (e.g., a register file, an integer register file or an integer file). In addition to the integer execution unit(s), the integer register files are also coupled to a bus for transfer of information to other units, such as memory. Thus, information can be loaded from memory to the integer register file, operated on by one or more integer execution unit (which calculation is returned to the register file) and the result ultimately stored back in the memory.
The floating point processing unit is configured similarly to the integer processing unit in that it also includes a number of registers which load and store information from other units such as memory. The floating point processing unit includes one or more execution units which operate based on floating point instructions. An advantage of a floating point unit is its ability to provide support for complex numerical and scientific calculations on data in floating point format.
In the course of numeric computation, it is often necessary to perform operations that resemble integer manipulation on floating point values, and it is occasionally necessary to perform operations that resemble floating point manipulation on integer values. Thus, a typical operation is to transfer particular data from one unit to the other, perform the computation, and then return the resultant data to the first unit. Some examples of such operations that couple floating point computation to integer computation are noted below. It should be appreciated that these examples are not the only operations that couple floating point and integer computations. Therefore, these examples are provided herein for illustration purposes only.
1) Exponent operation: Adding an integer value to an exponent of a floating point number to scale the number.
2) Sign operation: Reversing the sign of a number.
3) Mantissa operation: Inserting or deleting bits by OR'ing in (also referred to as “jamming”) explicit 1s (ones) or AND'ing in (also referred to as “jamming”) explicit 0s (zeros) into any of the mantissa positions in order to clamp a number to a certain defined value.
4) Boolean operation: Compounding Boolean values generated as a result of integer compares, as well as floating point compares.
5) Inter-conversion operation: Multiplying a floating point value with an integer value currently in the integer register file, which will require the movement of the integer value to the floating point register file and converting or translating it into floating point format.
In present microprocessors, single precision calculations have been performed on a single precision data format, which has been defined as having a bit length of 32 bits. The single precision data format includes 23 significand bits, 8 exponent bits and one sign bit. Additionally, a double precision data format has previously been implemented using a bit length of 64 bits. The double precision data format includes 52 significand bits, 11 exponent bits and one sign bit. Floating point operations have typicallly been performed on data in the double precision data format. Accordingly, integer register files have included integer registers of 32 bits in length, while floating point register files have included registers of 64 bits in length. The manipulation of single and double precision formats was simplified by the fact that the double precision format was exactly twice the length of the single precision format.
However, some microprocessors have extended the floating point capability to more than double precision. One microprocessor family developed by Intel Corporation (e.g., the 80386, 80486 and Pentium™ microprocessors) use an extended precision floating point format. The extended precision is an extension of the 64 bit double precision format and conforms to ANSI/IEEE (American National Standards Institute/The Institute of Electrical and Electronics Engineers) Standard 754 (1985), which is titled “IEEE Standard for Binary Floating-Point Arithmetic”. The extended precision format has been defined to have a bit length of 80 bits. However, while the floating point data format might have a bit length of 80 bits to accommodate the extended precision format, it is possible for future floating point formats to have a larger number of bits (e.g., 82 or more bits).
A current trend in microprocessor design is to extend the integer registers to have a bit length of 64 bits. Such a design requirement is prerequisite for microprocessors utilizing a 64-bit architecture (64 bits of addressing and data). Thus, integer units will utilize integer registers having 64 bits in length, while floating point units will utilize floating point registers having 80 bits or more bits in length (e.g., 82 bits in length). Accordingly, coupling of the integer register files of the integer processing unit and the floating point register files of the floating point processing units will involve transfers between 32 or 64 bit single or double precision memory format data values and 80 or 82 bit floating point format data values.
The above-mentioned copending applications disclose techniques for providing coupling between integer and floating point units. The coupling arrangements of these applications are referred to as “moderately coupled”, since the arrangement provides more coupling than a fully decoupled scheme, but less coupling than a fully coupled scheme. Although the arrangements of these applications disclose advantageous “moderately coupled” arrangements between the integer unit and the floating point unit, they do not address any data format translation between the memory format in which data are stored in the integer unit and the floating point format in which data are stored in the floating point unit. Thus, there is a need to provide a translation method to enhance the overall efficacy of the arrangements disclosed in the above-mentioned applications. Additionally, although these arrangements provide for transfer of double-extended memory format data and floating point format data between the integer unit and the floating point unit, no support is provided for direct transfers involving single precision memory format data and double precision memory format data between the integer unit and the floating point unit. Further, although logic circuits have previously been contemplated to translate between
Colon-Bonet Glenn
Doshi Guatam Bhawandas
Golliver Roger A.
Huck Jerome C.
Karp Alan Hersh
Institute for the Development of Emerging Architectures L.L.C.
Kenyon & Kenyon
Mai Tan V.
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