Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2002-04-22
2004-06-29
Nghiem, Michael (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
Reexamination Certificate
active
06757625
ABSTRACT:
BACKGROUND
Data transfer rates for digital electronics are increasing in all areas of wire-less and wire-line communication. Accordingly, digital data streams for video, high-definition television (HDTV), graphics, serial interface and many other applications are requiring higher bandwidth. The increase in digital data transfer rates is due in part to the growing popularity of the Internet and requires high speed interconnects between chips, functional boards and systems. As one of ordinary skill in the art appreciates, the data is digital, but the transmission media that the digital data travels along is analog.
The increase in bandwidth serves to render the digital communication circuits more susceptible to noise sources. In order to achieve the higher data transmission rates, the electronic circuits must improve immunity to electromagnetic interference, be capable of suppression of even order harmonics, and have a higher tolerance to non-ideal grounds. Use of balanced transmission topologies helps to achieve the foregoing. Accordingly, balanced transmission topologies are becoming more prevalent than in the past. Those of skill in the art familiar with the term “balanced topology” understand it to mean that there are two appropriately coupled conductor lines delivering an electrical signal to a single balanced port of a device. Two terminals form a single balanced port of a device, where each terminal is connected to one of the coupled conductors. As used herein, the term “device” refers to any device or circuit that exhibits electrical behavior. An analysis of balanced devices may be achieved by transforming the standard S-parameters of the device into mixed-mode S-parameters. The mixed-mode S-parameters describe differential mode and common mode signals propagating in a balanced structure. The differential mode occurs when two coupled conductors are driven with equal magnitude and 180 degrees out of phase with respect to each other. The common mode occurs when two coupled conductors have equal magnitude and are in phase with respect to each other. An ideal signal in a balanced structure is pure differential mode. Differential mode is advantageous because a high-speed digital differential receiver can produce a larger voltage, relative to the single-ended case, and represents a digital “1” where the voltages on the coupled conductors represent the state “1” and have an opposite polarity. Similarly, the differential receiver produces a smaller voltage, relative to the single-ended case, and represents a digital “0” where the voltages on the coupled conductors represent state “0” and have an opposite polarity. The purpose of coupling the conductors of a balance topology is to force any common mode signal, such as noise generated in the return path of the ground plane, to appear equally and in-phase on both conductors, thereby canceling at the digital differential receiver.
As part of the toolkit used by digital designers of devices having single-ended topologies, test, measurement, and analysis methods have been developed to help designers predict electrical behavior of a device that is comprised of multiple interconnected devices and elements from a model. After preparing a device design, the designer is able to mathematically predict the electrical behavior of the newly designed device and compare it against desired performance specifications for the device. In some cases, the predicted electrical behavior does not meet the desired performance specifications and, therefore, does not address the needs to which a device is being designed. In such a case, an electronic designer chooses to not prototype the newly designed device and proceeds to re-design the device to achieve the desired predicted behavior. Obviating the prototyping step for an under-performing device prevents waste of effort and money and helps to improve time to market with a better-performing product.
Agilent Application note 1364-1 entitled “De-embedding and Embedding S-Parameter Networks Using a Vector Network Analyzer” (herein “De-embedding/Embedding Application Note”), teaches a method termed “de-embedding”. The de-embedding method is used to determine the S-parameters of a device from a measurement of the device cascaded with two adapters, and a measurement of the two adapters themselves. The De-embedding/Embedding Application Note also teaches a method termed “embedding” for predicting electrical behavior of a modeled device. In the embedding process, a combination of device S-parameters and two adapter S-parameters helps to predict the behavior of the device in electrical combination with the adapters. The S-parameters used in the embedding process may be obtained from the de-embedding process or may be obtained through modeling a circuit and calculating the associated S-parameters. The use of the methods for embedding and de-embedding provide an important link between the computer aided design tools and the measurement tools in the electronic designers toolkit.
One limitation of the embedding method taught in the De-embedding/Embedding Application Note is the applications of the teachings are directed to single-ended devices. The prior art does not provide a method applicable to balanced devices, yet the use of balanced devices in the electronic design field is increasing. There is a need, therefore, for an embedding method applicable to balanced devices and circuits.
The use of devices and circuits having both balanced and single-ended device ports is also becoming more prevalent. Devices or circuits having both port styles are herein referred to as “mixed-port devices”. It is to be understood that the term “devices” refers to both devices and circuits. In mixed-port devices, it is common that the single-ended device ports and balanced ports interface a single-ended topology with a balanced topology to integrate single-ended and balanced topologies together as a single working system. There is a need, therefore, for a method of predicting electrical behavior of both pure balanced as well as mixed-port devices.
In many balanced topologies, the user desires to predict the electrical behavior of a device when it is embedded in a matching network. Typically, a model or S-parameter measurement represents the matching network. A Vector Network Analyzer (VNA) measures the S-parameters of linear devices. Because most commercially available VNAs are calibrated to a 50-ohm standard, the measured S-parameters, S
D
, are normalized to a 50-ohm characteristic impedance. The S-parameter matrix, S
D
, therefore, is a function of the characteristic impedance. Some balanced devices such as balanced filters require normalization to a characteristic impedance other than the conventional 50-ohms for single-ended device ports and the conventional 100-ohms for balanced ports. Additionally, the device impedance normalization might be different from port to port. Many commercial Electronic Design Automation software packages are available to model single-ended matching networks represented by a model and permit the model to be normalized to a user-specified impedance. No such commercial software package exists for balanced and mixed-port topologies. There is a need, therefore, for a method of embedding pure differential and mixed-port devices that permits normalization to an arbitrary impedance value.
REFERENCES:
patent: 4962359 (1990-10-01), Dunsmore
patent: 5025402 (1991-06-01), Winkelstein
patent: 5434511 (1995-07-01), Adamian et al.
patent: 5548221 (1996-08-01), Adamian et al.
patent: 5578932 (1996-11-01), Adamian
patent: 5793213 (1998-08-01), Bockelman et al.
patent: 6106563 (2000-08-01), Stengel et al.
patent: 6292070 (2001-09-01), Merrill
patent: 6347382 (2002-02-01), Nakayama et al.
patent: 6483415 (2002-11-01), Tang
patent: 6539344 (2003-03-01), Stengel et al.
patent: 2002/0003455 (2002-01-01), Vandersteen et al.
patent: 2002/0053899 (2002-05-01), Adamian et al.
patent: 2003/0001710 (2003-01-01), Tang et al.
patent: 2003/0135344 (2003-07-01), Martens
patent: 2003/0173975 (2003-09-01), Adamian
patent: 2003/0173
Adamian Vahe′ A.
Cole J. Bradford
Agilent Technologie,s Inc.
Nghiem Michael
Pretlow Demetrius
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