Method and tool for verification of algorithms ported from...

Data processing: software development – installation – and managem – Software program development tool – Testing or debugging

Reexamination Certificate

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C717S134000, C717S135000

Reexamination Certificate

active

10017777

ABSTRACT:
The invention relates to a software system and method for automatically verifying the correct execution of an application ported from one instruction set architecture (ISA) to another ISA. In this method, versions of the application are prepared for the two ISAs. Each version is then executed in a simulator or emulator for the appropriate ISA and the results of any change in memory made during the execution are compared. If each memory change made during the execution of the target version of the application is found to be equivalent to a memory change made during the execution of the source version of the application, the execution of the target (or ported) application is verifiably correct.

REFERENCES:
patent: 5444407 (1995-08-01), Ganapathy et al.
patent: 5724563 (1998-03-01), Hasegawa
patent: 5949993 (1999-09-01), Fritz
patent: 6081885 (2000-06-01), Deao et al.
patent: 6308263 (2001-10-01), Hayakawa et al.
patent: 6658578 (2003-12-01), Laurenti et al.
Guerra et al., “Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification”, ACM, pp. 964-969, Jun. 1999.
Levitt et al., “A Scalable Formal Verification Methodology for Pipelined Microprocessors”, ACM, pp. 1-6, 1996.
Bryant et al., “Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation” ASIAN '97 (1997), pp. 1-14.

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