Method and testing circuit for tracking transistor stress...

Details Method and testing circuit for tracking transistor stress... Method and testing circuit for tracking transistor stress...

2005-04-12

2005-04-12

Zarneke, David (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010

Reexamination Certificate

active

06879177

ABSTRACT:
A method and testing circuit are provided for tracking transistor stress degradation. A first array of P-channel field effect transistors (PFETs) is connected in parallel. The first array of PFETs is stressed by applying a low gate input and a high source and a high drain to the PFETs during a stress period. The first array of PFETs is tested by operating the PFETs in a saturated region during a test period. A reference array of PFETs is not stressed during the stress period. The reference array of PFETs is activated for testing to compare a saturated drain current performance with the first array of PFETs during the test period.

REFERENCES:
patent: 4970497 (1990-11-01), Broadwater et al.
patent: 6806117 (2004-10-01), King
patent: 20030042926 (2003-03-01), Rost

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