Method and systems for executing load instructions that...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass

Reexamination Certificate

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C712S217000

Reexamination Certificate

active

07376816

ABSTRACT:
A method is disclosed for executing a load instruction. Address information of the load instruction is used to generate an address of needed data, and the address is used to search a cache memory for the needed data. If the needed data is found in the cache memory, a cache hit signal is generated. At least a portion of the address is used to search a queue for a previous load instruction specifying the same address. If a previous load instruction specifying the same address is found, the cache hit signal is ignored and the load instruction is stored in the queue. A load/store unit, and a processor implementing the method, are also described.

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Park, Ooi & Vijaykumar; Reducing Design Complexity of the Load/Store Queue; Dec. 3, 2003; IEEE Computer Society; International Symposium on Microarchitecture; pp. 411-422.

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