Method and system using a common reset and a slower reset clock

Details Method and system using a common reset and a slower reset clock Method and system using a common reset and a slower reset clock

2001-07-24

2003-08-26

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S145000, C327S099000

Reexamination Certificate

active

06611158

ABSTRACT:

FIELD OF THE INVENTION
The present device relates generally to electronic systems and, more particularly, to electronic systems and components benefiting from different reset strategies.
BACKGROUND OF THE INVENTION
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. In most modem electronic devices, these circuits have been integrated in large numbers to realize increased capabilities. These efforts have resulted in an ever-increasing proliferation of customized chips, with each chip serving a unique function and application. This, in turn, has lead to various efforts to design and successfully test chips efficiently and inexpensively.
The design and development cycle time for large-scale systems can be shortened by using previously designed components, or modules, and coordinating the functionality of the modules to accommodate the overall design goal of the large-scale systems. Such modules, having been designed for systems having differing reset requirements, often have differing clock and timing constraints. Some modules, for example, employ an asynchronous reset scheme, a synchronous reset scheme or a mix of both. Others employ a positive-edge-triggered clocking scheme, a negative-edge-triggered clocking scheme, a level sensitive scheme, a multi-phased scheme, and so on.
In like manner, the convention used for resetting each module may differ. For each module, the reset strategy employed introduces timing constraints relative to the system's particular clocking scheme. Examples of such timing constraints include: a synchronous reset must arrive at the module for a specified duration before the active edge of the clock and/or be held at its active state for a specified duration after the clock edge; an asynchronous reset should not be released in close proximity to a change of clock state in a level sensitive clocking design; a reset signal should not be asserted, or de-asserted, in close proximity to an assertion or desertion of a set signal; and the release of a reset signal is advantageously effected about simultaneously for all modules. From a systems viewpoint, the varying reset and clocking strategies produce a combinatorial complex set of design constraints.
To accommodate the varying clocking strategies among modules, conventional systems include a module-clock-generator that produces the various clocking signals at appropriate frequency and phase relative to each other for proper system operation. Accommodation of the varying reset strategies is often less structured. Typically, because of the combinatorial nature of the problem, specific reset circuitry is designed for each module, or for each set of modules having a similar combination of reset and clock configurations. While the design of each reset circuit may not be unduly burdensome, the system-level design task of properly defining, configuring, and testing each of these circuits can be significant.
The use of specific, time-dependent, reset circuits also minimizes the likelihood that systems designed with such circuits will “scale” as technologies change, or as other features are added to the system. Similarly, the use of such a system as a future module in a larger system will only exacerbate the problems associated with modules having differing reset strategies and timing constraints.
SUMMARY OF THE INVENTION
The present invention is directed to a reset method and circuit for a clocked logic system that responds to a system reset by driving a common reset and reset clock signal of reduced frequency to each circuit module and controls reset de-assertion with respect to the common reset clock signal, and is particularly useful in addressing applications and problems discussed above. For example, a digital circuit arrangement can control the clock signal to the circuits to provide the clock signal at a first frequency during a reset mode, and at a second frequency after the reset mode, the first frequency being less than the second frequency. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to another example embodiment of the present invention, a plurality of circuit modules adapted to enable internal resets in response to an external reset signal using a method that addresses the previously-discussed applications and problems. A reset mode is initiated (an internal reset signal is asserted) in response to a system reset signal. Clock signals sent to each circuit module are controlled in response to the reset mode. A first frequency is provided during the reset mode as a reset clock signal, and a plurality of second frequencies are provided after the reset mode. The first frequency is at least as slow as the slowest frequency of the plurality of second frequencies. The reset mode is synchronized to the reset clock signal for each circuit module, and the synchronized reset signal is sent to reset each circuit module. When the system reset is disabled, and after a time delay of N reset clock cycles, the reset mode is exited. Each circuit module releases its internal reset when the reset mode is exited.
In a related example embodiment, the present invention is directed to a clocked logic system that is adapted to include a reset for a plurality of circuit modules in a manner. The clocked logic system includes a plurality of digital circuits arranged in a plurality of circuit modules. Each circuit module operates on a clock signal at one of a plurality of first frequencies. A clock module generates a reset clock signal at a second frequency, the second frequency being at least as slow as the slowest frequency of the plurality of first frequencies. A reset logic module controls assertion of an internal reset signal to each circuit module in response to a system reset signal and controls de-assertion of the internal reset signal to each circuit module with reference to the reset clock signal. A clock selector module switches the plurality of circuit modules to operate on the reset clock signal in response to the internal reset signal. A synchronization module is coupled to each one of the plurality of circuit modules and has a reset input port coupled to the reset module. The synchronization modules are adapted to synchronize the internal reset signal to the reset clock signal at each circuit module. The circuit modules are adapted to enable internal resets in response to an internal reset signal.
In another related example embodiment, a reset circuit is adapted to reset a plurality of circuit modules. The reset circuit includes a reset module adapted to generate an internal reset signal in response to a system reset signal, and a clock module having a clock selection switch. The clock module has an external clock reference and at least one clock module output for each of the plurality of circuit modules. The clock module provides a reset clock signal to each of the circuit modules via the clock module selection switch in response to the generated internal reset signal. The frequency of the clock module is selectable to an external clock reference.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.


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