Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-12-21
2004-08-24
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C205S123000
Reexamination Certificate
active
06780772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology and, more particularly, to techniques for removing metal from the surface of a patterned workpiece having fragile layers, without disturbing the structural integrity of the fragile layers and the wiring structure.
2. Description of the Related Art
Removal of excess material in a uniform manner from the surface of coated patterned substrates has wide range of applications. One of these applications is in the field of integrated circuit manufacturing. Conventional semiconductor devices such as integrated circuits generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide, and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling a conductor such as copper in features or cavities etched into the dielectric interlayers by a metallization process. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using features such as vias or contacts.
In a typical interconnect fabrication process, first an insulating interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches, pads, and vias in the insulating layer. Then, a metal such as copper is deposited on the substrate through a metallization process to fill all the features. The preferred method of copper metallization process is electroplating.
FIG. 1
illustrates a cross-sectional view of a surface region of an exemplary substrate
102
such as a wafer with features
104
such as trenches and vias formed into the insulating, or dielectric, layer
110
of the substrate
102
. In conventional deposition processes, a barrier layer
108
, and then, in the case of copper deposition, a very thin copper, or copper alloy, seed layer
112
are coated onto the insulating layer
110
and into the features
104
. As shown in
FIG. 2
, a material
106
, typically a metal such as copper (Cu), is deposited on the wafer
102
surface. Typically, the goal of a planarization process is to remove the metal
106
from the top surface of the wafer
102
, leaving the metal
106
only in the features
104
. This is presently achieved by a polishing technique such as chemical mechanical polishing (CMP), electropolishing, etching, or a combination of these techniques. The polishing techniques are conducted to remove the excess material
106
layer or material overburden and other conductive layers
112
,
108
that are above the top surface of the insulating layer
110
of substrate
102
.
With a patterned substrate
102
that has features
104
, the metal
106
when deposited onto the substrate
102
will tend to align to the features
104
, leaving valleys
114
in a top surface
116
of the metal
106
layer. In most commonly used CMP approaches, the surface of the substrate
102
is contacted with a pad and the pad is moved with respect to the surface. Companies such as 3M, Rodel, and Universal Photonics supply CMP pads of various types to the industry. The role of the pad is to polish the surface of the substrate
102
and to remove the material
106
on the surface with the help of, for example, a chemical solution or a slurry containing abrasive particles. When CMP techniques are used to remove a portion of the metal layer, the dielectric layer
110
of the substrate
102
receives uneven pressure from a polishing tool, such as the polishing pad, due to the valleys
114
in the metal
106
layer. Also, the resulting force from the CMP polishing pressures can easily exceed the fracture strength of the dielectric, or of any of the metal-dielectric interfaces. For this reason, fragile insulators and many low dielectric constant (&kgr;) films used as the dielectric layer
110
are easily damaged during CMP operations on metals
106
such as copper.
FIG. 3A
shows the cross-section of the same substrate
102
after, for example, a CMP technique has been applied and the excess metal
106
and the barrier layer
108
outside the features
104
have been removed. The substrate
102
is planarized so that the metal layer
106
is only in the features
104
, but the dielectric layer
110
of the substrate
102
has been damaged. As illustrated in
FIG. 3A
, defects such as cracks
118
are present in the dielectric layer
110
. As another example of defects,
FIG. 3B
shows the cross-section of the same substrate
102
after, for example, an electropolishing technique has been applied and a thin layer of excess metal
106
a
outside the features
104
is left behind. The topographic features, valleys
114
, in the metal
106
layer have been effectively transferred into the features
104
, leading to defects. The electropolished substrate
102
exhibits discontinuities between the metal
106
a
outside of the features
104
and the metal
106
within the features
104
. Defects and damage to the fragile dielectrics in workpieces, for example, semiconductor wafers, as in
FIG. 3A
, and defects such as surface discontinuities due to uneven polishing, as in
FIG. 3B
, can render the workpieces unusable for their intended purpose.
Avoiding damage to fragile dielectric films on workpiece and substrates presents a challenge for state of the art CMP techniques. The higher the polishing pressure, the higher the metal removal rates are during CMP operations. Higher polishing pressures of, for example, three to six pounds per square inch (psi), while practical for strong dielectric films such as silicon dioxide, silicon nitride, and alumina, are problematic for many films with low dielectric constants, such as SOX, SILK, diamond like carbon (DLC), and their likes, let alone porous dielectrics. This is because they tend to be more fragile than silicon dioxide. In general, CMP operations that occur at low pressures, for example, less than three psi, do minimize the damage to the fragile dielectrics, but the operations result in lower metal removal rates, hence lower process throughput and higher operating costs.
It is also known to us an electrochemical mechanical deposition (ECMD) process, or a combination ECMD and electrochemical mechanical etching (ECMD/ECME) process to obtain a planar conductive surface over what had previously been a non-planar conductive layer, as described, for example, in U.S. Pat. No. 6,176,992. While usage of an ECMD process or an ECMD/ECME process is advantageous, having other processes that can also provide planarization are desirable.
To this end, it would be desirable to have other methods and systems for providing material removal and planarization of the surface of a substrate such as a semiconductor wafer surface that preserves the structural integrity of the dielectric layer, particularly in the case of fragile dielectric film layers.
SUMMARY OF THE INVENTION
By way of introduction only, the presently preferred embodiments described herein include systems and methods for providing material removal and planarization of the surface of a workpiece such as, for example, a semiconductor device or wafer, while preserving and improving the structural integrity of the dielectric layer on the workpiece and the entire wiring structure.
Systems and methods to operate upon a nonplanar top surface of a conductive surface layer of a workpiece, so as to, for example, preserve the structural integrity of a dielectric film layer disposed below the conductive surface layer, are presented. According to one aspect of the present invention, a layer of conducting material such as a conducting paste, an emulsion of a conducting material, or a slurry of a conducting material is appli
Basol Bulent M.
Talieh Homayoun
Uzoh Cyprian E.
Chen Kin-Chan
Nutool, Inc.
Pillsbury & Winthrop LLP
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