Method and system to monitor, debug, and analyze performance...

Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C717S104000, C703S022000

Reexamination Certificate

active

08032329

ABSTRACT:
Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.

REFERENCES:
patent: 5948089 (1999-09-01), Wingard et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6330225 (2001-12-01), Wingard et al.
patent: 6505260 (2003-01-01), Chin et al.
patent: 6578117 (2003-06-01), Weber
patent: 6662251 (2003-12-01), Brock et al.
patent: 6976106 (2005-12-01), Tomlinson et al.
patent: 7149829 (2006-12-01), Weber et al.
patent: 7165094 (2007-01-01), Weber et al.
patent: 2004/0210696 (2004-10-01), Meyer et al.
patent: 2007/0162268 (2007-07-01), Kota et al.
patent: 2008/0005713 (2008-01-01), Singh et al.
patent: 2008/0133489 (2008-06-01), Armstead et al.
patent: 2009/0150857 (2009-06-01), Srinivasan et al.
patent: 2010/0057400 (2010-03-01), Chou et al.
Drew Wingard, Sonics, Inc., “Sonics SOC Integration Architecture”, P1500 Presentation, Jan. 28, 1999, pp. 1-25.
Wolf-Dietrich Weber, Sonics, Inc., “Efficient shared DRAM Subsystems for SOC's”, Systems on IC's www.sonicsinc.com, Copyright 2001, Sonics, Inc., pp. 1-6.
OCP International Partnership, “Open Core Protocol Specification”, Release 1.0 OCP-IP Confidential, Document Revision 1.1.1, Copyright 2001, pp. 184 total.
Alan, Kamas, The Systemc OCP Models, An Overview of the SystemC Models for the Open Core Protocol, 2004, pp. 1-30.
Anssi Haverinen, et al, White Paper for SystemC (TM) based SoC Communication Modeling for the OCP (TM) Protocol, V1.0, Oct. 14, 2002, pp. 1-39.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system to monitor, debug, and analyze performance... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system to monitor, debug, and analyze performance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system to monitor, debug, and analyze performance... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4293127

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.