Method and system to improve single synthesizer setting times fo

Details Method and system to improve single synthesizer setting times fo Method and system to improve single synthesizer setting times fo

1997-09-05

2000-02-22

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

369 59, G11B 509

Patent

active

060287276

ABSTRACT:
A system and method is disclosed in which a circuit is provided to improve the settling performance of synthesizers used in read/write channel applications when the synthesizer is required to switch frequencies by a small percentage quickly. This is useful in read channel applications where the clock recovery is performed using an all-digital PLL. A digital timing recovery scheme is utilized in which one data frequency synthesizer provides both write and read frequencies. The read frequency is set higher than the write frequency to allow for oversampling when reading data from the storage medium. When changing from a write to read frequency or vice-versa the frequency synthesizer rapidly settles to the new frequency. The frequency synthesizer includes a phase locked loop which utilizes a controllable oscillator. The phase locked loop divisors are changed to obtain the desired frequency changes. An input signal to the controllable oscillator is also changed in order to obtain the rapid settling times. In one embodiment the oscillator is a current controlled oscillator and the control current to the oscillator is modified based on whether the data frequency synthesizer is utilized for a read operation or a write operation.

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