Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
2004-12-13
2008-12-16
Liu, Shuwang (Department: 2611)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C326S046000
Reexamination Certificate
active
07466783
ABSTRACT:
Embodiments of the invention relate to a method and system to implement a DDR interface, such as a high-speed encode/decode interface. In one embodiment, a method of encoding data comprises the acts of (1) receiving a first signal, a second signal, and a first clock signal common to the first and second signals; (2) detecting rising edges and falling edges of the first clock signal; and (3) generating a composite signal based at least in part on the first and second signals and the detected rising and falling edges. The composite signal is associated with a second clock signal that is generated based at least in part on the detected rising and falling edges and on a time delay relative to the first clock signal.
REFERENCES:
patent: 5418485 (1995-05-01), Duret et al.
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6215710 (2001-04-01), Han et al.
patent: 6240042 (2001-05-01), Li
patent: 6282132 (2001-08-01), Brown et al.
patent: 6396322 (2002-05-01), Kim et al.
patent: 6442102 (2002-08-01), Borkenhagen et al.
patent: 6525565 (2003-02-01), Young et al.
patent: 6538956 (2003-03-01), Ryu et al.
patent: 6621760 (2003-09-01), Ahmad et al.
patent: 6625241 (2003-09-01), Mejia
patent: 6757212 (2004-06-01), Hamamoto et al.
patent: 6791889 (2004-09-01), Peterson
patent: 2002/0003748 (2002-01-01), Fujita et al.
patent: 2002/0071334 (2002-06-01), Azim
patent: 2002/0147898 (2002-10-01), Rentschler et al.
patent: 2003/0042941 (2003-03-01), Wang et al.
patent: 2004/0103226 (2004-05-01), Johnson et al.
patent: 2004/0145962 (2004-07-01), Heo et al.
patent: 2004/0151053 (2004-08-01), Peterson
patent: 2004/0160833 (2004-08-01), Suzuki
patent: 2004/0163006 (2004-08-01), Rosen
patent: 2004/0174765 (2004-09-01), Seo et al.
Massoud Pedram, Qing Wu, Xunwei Wu, “A New Design for Double Edge Triggered Flip-flops,” Proceedings of the Asia and South Pacific Design Automation Conference, Feb. 1998, pp. 417-421.
Fugate Earl L.
Young Jason K.
Lexmark International Inc.
Liu Shuwang
Michael & Best & Friedrich LLP
Neff Michael R
LandOfFree
Method and system to implement a double data rate (DDR)... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system to implement a double data rate (DDR)..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system to implement a double data rate (DDR)... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4043673