Method and system of performing voltage drop analysis for power

Details Method and system of performing voltage drop analysis for power Method and system of performing voltage drop analysis for power

1997-09-30

1999-08-03

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750, G06F 1760, G06F 1900

Patent

active

059333588

ABSTRACT:
A method for testing for power supply network voltage drop violations in an integrated circuit through a computer simulation. First, the IC chip area is divided into a number of discrete regions. The simulation time is divided into a number of time segments. Next, the average aggregate currents corresponding to the transistors for each of the regions are calculated for each of the time segments. Only when a peak average current occurs for any one of the plurality of regions is the power supply network of the IC chip simulated for that time segment. Based on the voltage drops as determined by the power network simulation, violation conditions can be easily identified. Thus, the power network of the IC chip is simulated only when there is found to be high switching activity in some region of the chip. This is more efficient than performing power network voltage drop analyses all the time, even when switching activity throughout the chip is low and the likelihood of any voltage drop violations is very low.

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patent: 5598348 (1997-01-01), Rusu et al.
Freeman et al., "Automated Extraction of Spice Circuit Methods from Symbolic Gate Matrix Layout with Pruning," IEEE 23rd Design Automation Conf., 1986, pp. 418-424.

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