Method and system of jitter compensation

Details Method and system of jitter compensation Method and system of jitter compensation

2011-03-15

2011-03-15

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S034000, C331S17700V, C327S156000, C377S047000, C377S048000

Reexamination Certificate

active

07907016

ABSTRACT:
A phase locked loop frequency synthesizer with jitter compensation having a tapped delay line for compensating the jitter prior to passing a signal subject to jitter through a non-linearity; and, a ΣΔ modulator for generating, or a storing element for pre-generated storing, of a fractional pattern representing fractional weighting of a plurality of integer divisors, wherein the fractional pattern identifies one integer divisor, out of the plurality of integer divisors, at a time to be active.

REFERENCES:
patent: 5642082 (1997-06-01), Jefferson
patent: 6011815 (2000-01-01), Eriksson et al.
patent: 6346838 (2002-02-01), Hwang et al.
patent: 6515553 (2003-02-01), Filtol et al.
Swedish Patent Office, International Search Report for PCT/SE2004/000369, dated Jun. 8, 2004.

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