Method and system of interconnecting processors of a...

Details Method and system of interconnecting processors of a... Method and system of interconnecting processors of a...

2007-03-13

2007-03-13

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

10734340

ABSTRACT:
The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, (c) where the L processors comprise R non-overlapping partitions, (d) where each of the partitions comprises the processing unit of at least one of the processors, and (e) where L is an integer ≧2 and R is an integer ≧1. In an exemplary embodiment, the method and system include connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture and setting the connected L switches thereby interconnecting each of the partitions as a torus.

REFERENCES:
patent: 5715391 (1998-02-01), Jackson et al.
Fujii, Tetsurou and Sadayasu Ono. Interconnection Network Switch Design for Parallel DSP Systems. IEEE: 1992.
Reed, Daniel A. and Richard M. Fujimoto. Multiprocessor Networks: Message-Based Parallel Processing. MIT Press: 1987. p. 43, 46-52.

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