Method and system of evaluating PLL built-in circuit

Details Method and system of evaluating PLL built-in circuit Method and system of evaluating PLL built-in circuit

2002-12-16

2004-01-06

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C324S1540PB

Reexamination Certificate

active

06674301

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a PLL (Phase Locked Loop) built-in semiconductor integrated circuit (hereinafter, referred to as PLL built-in circuit), specifically to an evaluation method of a PLL built-in circuit, an evaluation system of a PLL built-in circuit, and a PLL built-in circuit containing a frequency divider.
Conventional test equipment stores a test pattern formed by combining an applied pattern outputted during a test and an expected pattern being an output of a normal tested device corresponding to the applied pattern in a memory. The test equipment operates on the basis of a system clock of a predetermined frequency. Generally, the PLL built-in circuit includes a PLL circuit and an F/F (Flip-Flop) circuit.
During a test, the test equipment inputs the applied pattern to the PLL built-in circuit synchronously with the system clock. Since the PLL circuit of the PLL built-in circuit operates at the speed of N times the system clock frequency, the output pattern of the PLL circuit switches at the frequency of N times the frequency of the applied pattern, and the output pattern of the F/F circuit (the output pattern of the PLL built-in circuit) also switches at the frequency of N times the frequency of the applied pattern. Receiving the output pattern from the PLL built-in circuit, the test equipment cares the output pattern with the expected pattern provided in advance, and thereby evaluates the PLL built-in circuit.
The first conventional evaluation method cares the output pattern with the expected pattern, at a timing of one time in one phase of the applied pattern outputted from the test equipment.
The second conventional evaluation method cares the output pattern with the expected pattern, at a timing of four times in one phase of the applied pattern outputted from the test equipment.
However, in the first conventional evaluation method, although the output pattern changes four times in one phase of the applied pattern, the care is executed only one time in one phase, which means that only one-fourth the number of the output pattern is cared; accordingly, the evaluation result involves a low reliability. And, the first conventional evaluation method executes the care only for one-fourth the number of the output pattern, and the evaluation of speed and access time of the PLL built-in circuit is impossible accordingly.
In the second conventional evaluation method, the care is executed four times in one phase of the applied pattern, but the number of the test pattern (combination of the applied pattern and the expected pattern) becomes four times the number with the case of the first conventional evaluation method, and in consequence the testing time becomes N times.
SUMMARY OF THE INVENTION
The invention may provide an evaluation method of a PLL built-in circuit, an evaluation system of a PLL built-in circuit, and a PLL built-in circuit that allow various characteristic evaluations without increasing test patterns with high reliability of the evaluation results.
A method of evaluating a PLL built-in circuit according the present invention includes outputting an applied pattern signal from a test equipment synchronized with a system clock signal received by the test equipment, dividing the applied pattern signal into M/N frequencies by a frequency divider, wherein M and N are positive integers. The method further includes inputting the divided pattern signal into the PLL built-in circuit, inputting an output pattern signal outputted from the PLL built-in circuit into the test equipment and caring the output pattern signal with the applied pattern signal so as to evaluate the PLL built-in circuit. In the method according to the present invention, M and N are set in a manner that a frequency of the output pattern signal from the PLL built-in circuit is substantially equal to a frequency of the system clock signal.


REFERENCES:
patent: 4754216 (1988-06-01), Wong
patent: 5555278 (1996-09-01), Kondoh
patent: 5973571 (1999-10-01), Suzuki
patent: 6294935 (2001-09-01), Ott
patent: 6378098 (2002-04-01), Yamashita

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