Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
1998-06-12
2001-07-24
Donaghue, Larry D. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S216000, C712S217000
Reexamination Certificate
active
06266761
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The depicted illustrative embodiment relates to superscalar data processing systems and, in particular, to efficiently maintaining copies of values stored within a plurality of registers in a superscalar data processing system. Still more particularly, the illustrative embodiment relates to establishing within a superscalar data processing system a queue within which copies of values stored within a plurality registers are sequentially stored.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required. These multiple instructions may be executed in their original sequence intended by the programmer, or out of order in a sequence which is different in some way from the original sequence.
The overlap of the fetching and decoding of one instruction with the execution of a second instruction is called pipelining. In pipelined superscalar data processing systems, care must be taken to avoid dependencies where multiple instructions are fetched, decoded, and executed in a single cycle.
There are three types of data dependencies. A read-after-write hazard occurs when an instruction tries to read a source before a previous instruction writes it. A write after read hazard occurs when an instruction tries to write a destination before a previous instruction reads it. A write after write hazard occurs when an instruction writes a destination before a previous instruction writes it.
One solution to solving the dependence problem is to rename the logical registers associated with the instructions. By renaming the logical registers, each instruction within the cycle can be executed concurrently and correctly.
One problem in the design of microprocessors is the management of available resources. Resources typically become free after some period of time and then are available to be utilized again. Resources may include, among other types, execution units, buses, or registers. One type of register resource is a special-purpose register which is typically a register designated for a special purpose. The special-purpose registers contain control information such as the count or link registers included in the Power PC architecture.
Special-purpose registers may be difficult to manage during processing in superscalar data processing systems because each is a unique resource and because the programmer's model of sequential execution must be maintained.
Therefore a need exists for a method and system in a superscalar data processing system for efficiently maintaining copies of values stored within a register by storing copies within a queue and storing a queue entry identifier within an array.
SUMMARY OF THE INVENTION
It is therefore one object of the depicted illustrative embodiment to provide an improved superscalar data processing system.
It is another object of the illustrative embodiment to efficiently maintain copies of values stored within a plurality of registers in a superscalar data processing system.
It is yet another object of the illustrative embodiment to provide a method and system within a superscalar data processing system for establishing a queue within which copies of values stored within a plurality registers are sequentially stored.
The foregoing objects are achieved as is now described. A method and system in an information processing system are disclosed for efficiently maintaining copies of values stored within a plurality of registers. The information processing system includes first circuitry, second circuitry, and a plurality of buffers. The first circuitry processes an execution state of a first type of instruction which always specifies a destination of at least one of a first type of register or a second type of register and which outputs first information in response thereto. The first circuitry also processes an execution stage of a second type of instruction which always specifies a destination of only a third type of register and outputs second information in response thereto. The plurality of buffers are coupled to the execution circuitry for storing the output first and second information, wherein at least one of the buffers is for storing the output first information independent of which of the first and second types of registers is specified by the first type of instruction. The second circuitry is coupled to the buffers for processing a completion stage of the first type of instruction, and writing the stored first information into at least one of the first or a second type of register in response thereto. The second circuitry also processes a completion stage of the second type of instruction, and writes the stored second information into only the third type of register in response thereto.
The above as well as additional objectives, features, and advantages of the illustrative embodiment will become apparent in the following detailed written description.
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Carlson Michael David
Hoy Thomas Alan
Potter Terence Matthew
Putti David Domenic
Donaghue Larry D.
England Anthony V. S.
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
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