Patent
1995-01-04
1999-03-23
Coleman, Eric
39580017, 39580004, G06F 1580
Patent
active
058871837
ABSTRACT:
A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.
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Agarwal Ramesh Chandra
Groves Randall Dean
Gustavson Fred G.
Johnson Mark A.
Lyon Terry L.
Coleman Eric
Dillon Andrew J.
England Anthony V.S.
International Business Machines - Corporation
Russell Brian F.
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