Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2011-06-28
2011-06-28
Jacob, Mary C (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C716S106000, C717S124000
Reexamination Certificate
active
07970596
ABSTRACT:
An integrated design environment (IDE) is disclosed for forming virtual embedded systems. The IDE includes a design language for forming finite state machine models of hardware components that are coupled to simulators of processor cores, preferably instruction set accurate simulators. A software debugger interface permits a software application to be loaded and executed on the virtual embedded system. A virtual test bench may be coupled to the simulation to serve as a human-machine interface. In one embodiment, the IDE is provided as a web-based service for the evaluation, development and procurement phases of an embedded system project. IP components, such as processor cores, may be evaluated using a virtual embedded system. In one embodiment, a virtual embedded system is used as an executable specification for the procurement of a good or service related to an embedded system.
REFERENCES:
patent: 5197016 (1993-03-01), Sugimoto et al.
patent: 5548717 (1996-08-01), Wooldridge et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5946474 (1999-08-01), Skogby
patent: 5987243 (1999-11-01), Aihara
patent: 6052524 (2000-04-01), Pauna
patent: 6094654 (2000-07-01), Van Huben et al.
patent: 6263302 (2001-07-01), Hellestrand et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6594799 (2003-07-01), Robertson et al.
patent: 6618854 (2003-09-01), Mann
patent: 6760888 (2004-07-01), Killian et al.
patent: 2002/0038401 (2002-03-01), Zaidi et al.
patent: 2002/0138244 (2002-09-01), Meyer
patent: 2003/0069724 (2003-04-01), Schubert et al.
patent: 2003/0115564 (2003-06-01), Chang et al.
patent: 2004/0059678 (2004-03-01), Stefik et al.
patent: 2004/0226000 (2004-11-01), Finch
patent: 2004/0250083 (2004-12-01), Schwab
patent: 2005/0027973 (2005-02-01), Barry et al.
patent: 2005/0060549 (2005-03-01), England et al.
patent: 2005/0144641 (2005-06-01), Lewis
patent: 2005/0193280 (2005-09-01), Schubert et al.
patent: 2005/0234811 (2005-10-01), Herman et al.
patent: 2005/0273432 (2005-12-01), Stefik et al.
patent: 2005/0273433 (2005-12-01), Stefik et al.
patent: 0 772 140 (1997-05-01), None
patent: 0 867 820 (1998-09-01), None
Araki et al, “Rapid Prototyping with HW/SW Codesign Tool”, IEEE Conference and Workshop on Engineering of Computer-Based Systems, Mar. 7-12, 1999.
Mentor Graphics, “Seamless Co-Verification Environment User's and Reference Manual”, Software Version 3.0, Chapter 1 and Chapter 2 (Up Through “Running Multiple XRAY ISSs”), 1996-1999.
Hubert, Heiko, “A Survey of HW/SW Cosimulation Techniques and Tools”, Thesis Work, Electronic Systems Design Laboratory, Royal Institute of Technology, Jun. 1998.
Dalpasso et al, “Virtual Simulation of Distributed IP-Based Designs”, Proceedings of the 36th ACM/IEEE Conference on Design Automation, Jun. 21-25, 1999.
Dreike et al, “Introduction to Co-Simulation of Software and Hardware in Embedded Processor Systems”, Sandia National Laboratories, Embedded Systems Conference, Sep. 1996.
Domer et al, “Reuse and Protection of Intellectual Property in the SpecC System”, Proceedings of the Asia and South Pacific Design Automation Conference, Jan. 2000.
Chang et al, “Heterogeneous Simulation-Mixing Discrete Event Models with Dataflow”, Journal of VLSI Signal Processing, 15, pp. 127-144, 1997.
Liu et al, Software Timing Analysis using HW/SW Cosimulation and Instruction Set Simulator, 6th International Conference on Hardware Software Codesign, 1998.
Berry, Gerard. “An Implementation of Constructive Synchronous Programs in POLIS”, Nov. 2, 1998, pp. 1-22.
Hopes, Tim. “Hardware/Software Co-Verification, An IP Vendors Viewpoint”, Proc. of the International Conference on Computer Design: VLSI in Computers and Processors, 1998, Oct. 5-7, 1998, pp. 242-246.
Lavagno, Luciano. “Models of Computation for Embedded System Design”, Sep. 28, 1998, pp. 1-57.
Nadamuni, Daya. “Co-Verification Tools: A Market Focus”, Embedded Systems, Programming, Sep. 1999, Miller Freeman, vol. 12, No. 9, pp. 119-122.
Shah et al. “Target Processor and Co-Verification Environment Independent Adapter-A Technology to Shorten Cycle-Time for Retargeting TI Processor Simulators in HW/SW Co-Verification Environments”, Proc. of the 12th Annual IEEE International ASIC/SOC Conference, Sep. 15-18, 1999, pp. 37-41.
Yasuda et al. “A Top-Down Hardware/Software Co-Simulation Method for Embedded Systems Based upon a Component Logical Bus Architecture”, Design Automation Conference, Proc. of the ASP-DAC Asia and South Pacific, Feb. 10-13, 1998, IEEE, pp. 169-175.
“Datasheet: EnWave Digital Communications Design System”, Cadence Design Systems, Inc., 1997, 5 pgs.
“Datasheet: Interactive Simulation Library”, Cadence Design Systems, Inc., 1997, 3 pgs.
“Datasheet: Signal Processing Workstation with Convergence Simulation Architecture”, Cadence Design Systems, Inc., 1997, 10 pgs.
Bade Stephen L.
Ben-Chorin Shay
Caamano Paul
Montoreano Marcelo E.
Taggu Ani
Bever Hoffman & Harms LLP
Harms Jeanette S.
Jacob Mary C
Synopsys Inc.
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