Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-12-10
2004-08-03
Abraham, Fetsum (Department: 2826)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C257S347000
Reexamination Certificate
active
06770512
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method and system for improving the staining of conductive structures, such as those made of copper, on silicon on insulator semiconductor devices.
BACKGROUND OF THE INVENTION
Silicon on insulator (SOI) semiconductor devices are increasingly utilized. A SOI semiconductor device includes a semiconductor substrate, or bulk silicon. On the semiconductor substrate is an insulating layer, typically silicon dioxide. The insulating layer is known as the box layer. On the box layer is silicon that is typically p-doped. The devices, such as memory cells, transistors, and junctions, are formed on the silicon. Conductive structures, such as interconnects and contacts, electrically connect devices within the SOI semiconductor device. Typically, the conductive structures are composed of copper.
Often, the circuits in SOI semiconductor devices include one or more faults. In particular, one or more of the conductive structures may have a fault such as a short or an open circuit. In order to investigate the nature of the faults, the SOI semiconductor device is deprocessed. Conventional methods for failure analysis include exposing the conductive structures in cross sections for investigation. Once cross sections are prepared from the SOI semiconductor device, the cross sections are stained, or etched. Staining typically involves treating the cross section with a conventional stain, or selectively etchant. Portions of the SOI semiconductor device are removed by the conventional stain. Staining is used to allow the experimenter to more clearly view the conductive structures. In particular, removal of the silicon
Although conventional cross-section preparation and staining can allow investigation of the conductive structures in an SOI semiconductor device, one of ordinary skill in the art will readily recognize that conventional stains do not simplify distinguishing the conductive structures from the remainder of the SOI semiconductor device. In particular, conventional stains tend to stain unwanted portions of the SOI semiconductor device. For example, most conventional stains attack structures formed of silicides and silicon nitride, such as silicon nitride spacers. Staining of both the conductive structures and other portions of the SOI semiconductor device makes the conductive structures difficult to distinguish. As a result, an investigator may be unable to detect failures in the conductive structures. For example, the presence of open circuits in interconnects or short circuits between interconnects may be overlooked. As a result, it may be difficult or impossible to adequately perform failure analysis.
Accordingly, what is needed is a system and method for improving failure analysis of conductive structures on a SOI device. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for performing failure analysis on a SOI semiconductor device. The SOI device includes a plurality of conductive structures in a silicon region. The silicon resides on a box insulator, which resides on a silicon substrate. The method and system comprise providing a cross-section of the SOI semiconductor device. The cross-section of the SOI semiconductor device includes a portion of the plurality of conductive structures. The method and system also comprise staining the cross-section of the SOI semiconductor device using a stain. The stain etches the silicon region in the SOI semiconductor device without etching a remaining portion of the SOI semiconductor device not composed of silicon.
According to the system and method disclosed herein, the present invention provides a method and system for performing failure analysis on the conductive structures in an SOI device.
REFERENCES:
patent: 5421958 (1995-06-01), Fathauer et al.
Mahanpour Mehrdad
Masoodi Mohammad
Tracy Bryan M.
Abraham Fetsum
Advanced Micro Devices , Inc.
Winstead Sechrest & Minick P.C.
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