Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
1999-06-30
2002-07-02
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C714S051000
Reexamination Certificate
active
06415378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved data processing system and, in particular, to a method and system for debugging the execution of a processor within a data processing system.
2. Description of Related Art
In typical computer systems, system developers desire optimization of software execution for more effective system design. Usually, studies are performed to determine system efficiency in a program's access patterns to memory and interaction with a system's memory hierarchy. Understanding the memory hierarchy behavior helps optimize the system through the development of algorithms that schedule and/or partition tasks as well as distribute and structure data. Similarly, the utilization of a processor can be studied to understand the manner in which the execution of a program invokes various functions within the processor.
Many modern processors have the ability to execute instructions in an execution pipeline consisting of multiple stages. An instruction is fetched into a first stage and progresses from one stage to the next stage. Each unit along the pipeline operates on a different instruction by performing a single task for a particular stage of execution of the particular instruction. In addition, many modern processors execute instructions out-of-order with respect to the sequence in which the programmer coded the instructions or in which the compiler generated the instructions. As a result, instructions are completed, or retired, in order but execute as their data dependencies allow.
The debugging of hardware requires knowledge about the use of processor resources. However, in a processor with out-of-order execution of instructions, the out-of-order characteristic increases the difficulty of debugging the execution of a set of instructions. The ability to process instructions out-of-order may be disabled, but this attempt to debug an instruction may mask or avoid the very problem being debugged.
Therefore, it would be advantageous to have a method and system for accurately monitoring the use of resources within a processor that performs out-of-order execution of instructions. It would be further advantageous to have a method and system for providing knowledge of when the stages of a pipeline execute.
SUMMARY OF THE INVENTION
The present invention provides a method and system for debugging the execution of an instruction within an instruction pipeline. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.
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Profile Me: Hardware Support For Instruction Level Profiling On Out Of Order Processors; Dean et al.
Davidson Joel Roger
Laurens Judith K.
Mericas Alexander Erik
Reick Kevin F.
Tendler Joel M.
Coleman Eric
Emile Volel
International Business Machines - Corporation
Nichols Michael R.
Yee Duke W.
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