Method and system for the design verification of logic units and

Details Method and system for the design verification of logic units and Method and system for the design verification of logic units and

1995-06-06

1996-10-22

Voeltz, Emanuel T.

Boots, shoes, and leggings

364488, 364489, 371 27, 324 731, G05B 19045

Patent

active

055684076

ABSTRACT:
A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

REFERENCES:
patent: 4688222 (1987-08-01), Blum
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patent: 5212443 (1993-05-01), West et al.
patent: 5225772 (1993-07-01), Cheung et al.
patent: 5243273 (1993-09-01), McAuliffe et al.
patent: 5293374 (1994-03-01), Eidson
"Random Finite State Machines", IBM Technical Disclosure Bulletin, vol. 37, No. 03, Mar. 1994, pp. 223-224.

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