Method and system for the design of pipelines of processors

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

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Reexamination Certificate

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07107199

ABSTRACT:
A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.

REFERENCES:
patent: 5455938 (1995-10-01), Ahmed
patent: 5742814 (1998-04-01), Balasa et al.
patent: 5764951 (1998-06-01), Ly et al.
patent: 6064819 (2000-05-01), Franssen et al.
patent: 6078745 (2000-06-01), De Greef et al.
patent: 6298071 (2001-10-01), Taylor et al.
patent: 6389382 (2002-05-01), Tanaka et al.
patent: 6449747 (2002-09-01), Wuytack et al.
patent: 6594814 (2003-07-01), Jou et al.
patent: 6609088 (2003-08-01), Wuytack et al.
patent: 6732297 (2004-05-01), Oura
patent: 6772415 (2004-08-01), Danckaert et al.
patent: 6839889 (2005-01-01), Liu
patent: 6853968 (2005-02-01), Burton
patent: 6934250 (2005-08-01), Kejriwal et al.
patent: 2002/0032559 (2002-03-01), Hellestrand et al.
patent: WO01/59593 (2001-08-01), None
Park, Sehwa: A software package foe synthesis of pipelines from behavioral specifications, IEE Transaction on computer aided design of integrated circuits, Mar. 1988, pp. 356-370.
U.S. Appl. No. 10/223,224, Schreiber.
U.S. Appl. No. 10/284,844, Schreiber, et al.
U.S. Appl. No. 10/284,965, Gupta, et al.
Christine Eisenbeis, et al., “A Strategy for Array Management in Local Memory,” (Jul. 1990) pp. 1-40.
J. Rosseel, et al., “An Optimisation Methodology for Array Mapping of Affine Recurrence Equations in Video and Image Processing,” IEEE, pp. 415-426 (1994).
S. Malik, “Analysis of Cyclic Combinational Circuits,” Short Papers IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 13, No. 7, (Jul. 1994) pp. 950-956.
A. Srinivasan, et al. “Practical Analysis of Cyclic Combinational Circuits,” IEEE 1996 Custom Integrated Circuits Conference, pp. 381-384.
Guest Editorial, IEEE Transactions on Computer-aided Design of Ingegrated Circuits and Systems, vol. 18, No. 1, (Jan. 1999) pp. 1-2.
K. Danckaert, et al. “Strategy for Power-Efficient Design of Parallel Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 2, (Jun. 1999) pp. 258-265.
F. Vermeulen, et al., “Extended Design Reuse Trade-Offs in Hardware-Software Architecture Mapping,” (2000) pp. 103-107.
R. Schreiber, et al., “High-Level Synthesis of Nonprogrammable Hardware Accelerators,” IEEE (2000) pp. 1-12.
S. Mahike, et al., “Bitwidth Cognizant Architecture Synthesis of Custom Hardware Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, No. 11, (Nov. 2001) pp. 1355-1371.
P. R. Panda, et al., “Data and Memory Optimization Techniques for Embedded Systems,” ACM Transactions on Design Automation of Electronic Systems, vol. 6, No. 2, (Apr. 2001) pp. 149-206.
S. Meftali, et al., “An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip,” (2001) pp. 19-24.
T. Van Achteren, et al., “Data Reuse Exploration Techniques for Loop-dominated Applications,” Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition , IEEE Computer Society, (Jan. 2002).
“Omega Project Source Release, version 1.2,” (Aug. 2002), [on-line] [Retrieved on Jul. 16, 2002] Retrieved from: http://www.cs.umd.edu/projects/omega/release-1.2.html, pp. 1-2.
Seeds for Tomorrow's World—IMECnology, [on-line] [Retrieved on Jun. 12, 2002] Retrieved from http://www.imec.be/.
S. Meftali, et al., “An Optimal Memory Allocation for Application-Specific Multiprocessor System-on-Chip,” Proceedings of the International Symposium on Systems Synthesis—vol. 14, [on-line] [Retrieved on Jun. 12, 2002] Retrieved from: .../citation.cfm?id= 500006&coll= portal&dl= ACM&CFID= 2929668&CFTOKEN= 57821200.
G. Havas, et al. “Extended GCD and Hermite Normal Form Algorithms Via Lattice Basis Reduction,” Experimental Mathmatics, v. 7 (1998).
PCT Written Opinion—New Citations—PCT/US2003/032340 filed Oct. 10, 2003.
McFarland, M C et al—“The High-Level Synthesis of Digital Systems”—Proceedings of the IEEE vol. 78 No. 2—Feb. 1, 1990—pp. 301-318.
Park, N et al—“Sehwa: A Software Package for Synthesis of Pipelines From Behavioral Specification”—IEEE Transactions vol. 7 No. 3 Mar. 1998—pp. 356-370.
R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 31(2), Jun. 2002.
J. Steensma, B. Vanhoof, F. Catthoor, H. De Man, Symbolic Macro Test for DSP Systems applied to a Voice Coder Application, Workshop on VLSI Signal Processing, pp. 215-223, Oct. 1993.
Anant Agarwal, David Kranz, Automatic Partitioning of Parallel Loops and Data Arrays for Distributed Shared Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, (1995).
R. Trancon, M. Bruynooghe, G. Janssens, F. Catthoor, Storage Size Reduction by In-place Mapping of Arrays, VMCAI, pp. 167-181, (2002).
P.R. Panda, F. Catthoor, N.D.Dutt, K. Dranckaert, E. Brockmeyer, C. Kulkarni, A. Vandecappelle, P.G. Kjeldsberg, Data and Memory Optimization Techniques for Embedded Systems, ACM Trans. Design Autom. Electr. Syst. Vo. 6, No. 2, pp. 149-206, Apr. 2001.

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