Method and system for testing self-timed circuitry

Details Method and system for testing self-timed circuitry Method and system for testing self-timed circuitry

1996-12-13

1999-02-09

Beausoliel, Jr., Robert W.

Excavating

326 93, G01R 3128

Patent

active

058704116

ABSTRACT:
From a first circuit, first information is output in response to acknowledgement signals. From a second circuit, second information and the acknowledgement signals are output. The second information and the acknowledgement signals are output in response to the second circuit receiving portions of the first information from the first circuit during a functional mode of operation. The portions and the acknowledgement signals are output asynchronously with respect to one another. From a third circuit, third information is output in response to the second information. From a test circuit, the second information output from the second circuit is specified, so that the third circuit outputs the third information in response to the specified second information independent of the first information output from the first circuit during a test mode of operation.

REFERENCES:
patent: 5121003 (1992-06-01), Williams
patent: 5289403 (1994-02-01), Yetter
patent: 5386585 (1995-01-01), Traylor
patent: 5394403 (1995-02-01), Klein
patent: 5446695 (1995-08-01), Douse et al.
patent: 5450020 (1995-09-01), Jones et al.
patent: 5471428 (1995-11-01), Baroni et al.
patent: 5615169 (1997-03-01), Leung
patent: 5703821 (1997-12-01), Baroni et al.
patent: 5703823 (1997-12-01), Douse et al.
patent: 5710910 (1998-01-01), Kehl et al.

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