Method and system for testing self-timed circuitry

Details Method and system for testing self-timed circuitry Method and system for testing self-timed circuitry

1996-12-13

1999-06-15

Tu, Trinh L.

Excavating

G01R 3128

Patent

active

059129000

ABSTRACT:
From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.

REFERENCES:
patent: 5083049 (1992-01-01), Kagey
patent: 5121003 (1992-06-01), Williams
patent: 5289403 (1994-02-01), Yetter
patent: 5394403 (1995-02-01), Klein
patent: 5450020 (1995-09-01), Jones et al.
patent: 5471428 (1995-11-01), Baroni et al.
patent: 5475320 (1995-12-01), Ko
patent: 5546354 (1996-08-01), Partovi et al.
patent: 5698996 (1997-12-01), Ko

Affiliated with

Also associated with

Rating

Method and system for testing self-timed circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for testing self-timed circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for testing self-timed circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-407413