Method and system for testing memory

Details Method and system for testing memory Method and system for testing memory

1997-09-19

1998-09-29

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058155090

ABSTRACT:
The invention comprises a method and system for testing memory in an interface system 10 coupling a parallel host bus 30 to a serial bus 20. The system comprises a random access memory 70 having a plurality of memory locations for temporarily storing data received from either the parallel host bus 30 or the IEEE 1394 serial bus 20, the random access memory 70 being logically divided into a transmit memory portion and a receive memory portion. The interface also comprises a transmission control unit 40 operable to control transmission of data from the parallel host bus 30 to the IEEE 1394 serial bus 20. The transmission control unit 40 is further operable to access the transmit memory portion of the random access memory 70. The interface also comprises a reception control unit 50 operable to control reception of data by the parallel bus 30 from the serial bus 20. The receive control unit 50 is further operable to access the receive memory portion of the random access memory 70. The interface further comprises a test unit 60 operable to selectively obtain control of the random access memory 70 based on a control signal received from the parallel host bus 30; internally generate addresses for each memory location within the random access memory 70; control transmission of parallel data from each memory location associated with the internally generated addresses to the parallel host bus 30 for inspection; and selectively relinquish control of the random access memory 70 to allow transmission of data between the IEEE 1394 serial bus 20 and the parallel host bus 30.

REFERENCES:
patent: 4788683 (1988-11-01), Hester et al.
patent: 5428806 (1995-06-01), Pocrass

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