Method and system for testing an integrated circuit featuring sc

Details Method and system for testing an integrated circuit featuring sc Method and system for testing an integrated circuit featuring sc

1993-08-20

1996-01-16

Ramirez, Ellis B.

Excavating

371 27, G01R 3128

Patent

active

054854733

ABSTRACT:
The present invention provides for improved testing of an integrated circuit. In order to measure a test signal S from the integrated circuit 1 a multi-pattern is placed in a shift register. The multi-pattern is generated by overlaying at least two test patterns Ax and Bx. Therefore the signal S changes its state in response to only a small amount of shift operations.

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13th Annual Symposium on Fault-Tolerant Computing, Jun. 28-30, 1983 pp. 222-226 IEEE, New York, US; D. T. Tang et al, "Logic Test Pattern Generating Using Linear Codes".
Proceedings of the Intl. Test Conf., Sep. 10-14, 1990, pp. 670-679, IEEE, New York, US, S. Hellebrand, "Generating Pseudo-Exhaustive Vectors for External Testing".
Design for Contactless Testability in a Scan-Path Environment-Josef GroB, Torsten Gruning-1991-16 pages.

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