Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-07-19
2004-11-23
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S014000, C438S795000, C374S045000, C324S755090
Reexamination Certificate
active
06821796
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to manufacture of integrated circuit packages, and more particularly, to a method and system for temperature cycling at an interface between an IC (integrated circuit) die and an underfill material of an IC (integrated circuit) package that accurately reflects temperature cycling during operation of the integrated circuit on the IC die.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, an IC (integrated circuit) package
100
is comprised of an IC (integrated circuit) die
102
mounted to an IC (integrated circuit) package housing
104
with an underfill material
106
. The IC package
100
provides connection between pins
108
of the IC package
100
to nodes of the integrated circuit fabricated on the IC die
102
, as known to one of ordinary skill in the art of electronics. During operation of the integrated circuit on the IC die
102
, power is dissipated, and the IC die
102
heats up.
Temperature cycling is performed for assessing the effect of thermal stress on the IC package
100
as the temperature of the IC die
102
varies from a low-end temperature such as −65° Celsius to a high-end temperature such as 150° Celsius. Referring to
FIG. 2
, in the prior art, to assess the effect of the high-end temperature on the IC package
100
, the IC package
100
is placed within a heating chamber
110
. A heat source
112
within the heating chamber
110
changes the environmental temperature within the heating chamber
110
. Then, the temperature of the whole IC package
100
including the whole IC die
102
within the IC package
100
gradually heats up from being placed within the heating chamber
110
. Typically, the whole IC package
100
heats up to the enviromental temperature within the heating chamber
110
after the IC package
100
has been within the heating chamber for several minutes.
Referring to
FIG. 3
, an enlarged cross sectional view of the IC die
102
includes active device regions
122
fabricated from a front side
124
of the IC die
102
. The IC die
102
is comprised of a semiconductor material, such as silicon for example, for fabricating integrated circuit structures therein. The active device regions
122
are typically shallow from the front side
124
of the semiconductor die. For example, the active device regions
122
may be comprised of drain and source junctions of MOSFETs (metal oxide semiconductor field effect transistors) having depths in a range of hundreds of nanometers to micrometers, as known to one of ordinary skill in the art of integrated circuit fabrication.
A back side
126
of the semiconductor die
102
is opposite to the front side
124
of the semiconductor die
102
. In addition, an interlevel dielectric material
128
, comprised of silicon dioxide (SiO
2
) for example, is formed on the front side of the semiconductor wafer. The interlevel dielectric material
128
is comprised of the dielectric material through which interconnect structures are formed, and the interlevel dielectric material
128
is also comprised of encapsulating dielectric material, as known to one of ordinary skill in the art of integrated circuit fabrication.
Typically, within an IC package, the front side
124
of the IC die
102
is mounted to the IC package via an underfill material
130
, as known to one of ordinary skill in the art of IC package manufacture. The underfill material
130
is comprised of a material for bonding the IC die
102
to the housing of the IC package. The interlevel dielectric material
128
is disposed at the interface between the front side
124
of the IC die
102
and the underfill material
130
of the IC package.
FIG. 4
shows an example IC package named as a “flip-chip”
150
, as known to one of ordinary skill in the art of IC package manufacture. In the flip-chip IC package
150
, the IC die
102
is mounted to the IC package housing
106
with the underfill material
130
. Each of a plurality of pins
152
of the flip chip IC package
150
provides connection to a respective node of the integrated circuit on the IC die
102
via a respective one of a grid array of contact balls
125
. In the flip-chip IC package
150
, the front-side
124
of the IC die
102
is mounted to the underfill material
130
while the back side
126
of the IC die
102
is exposed. Referring to
FIGS. 3 and 4
, an interlevel dielectric material is formed on the front side of the IC die
102
mounted on the flip-chip IC package
150
(similar to the interlevel dielectric material
128
of FIG.
3
), and such an interlevel dielectric material
128
is at the interface between the front-side
124
of the IC die
102
and the underfill material
130
of the flip-chip IC package
150
.
Further referring to
FIGS. 3 and 4
, during operation of the integrated circuit on the IC die
102
, the front-side
124
of the IC die heats up rapidly as power is dissipated within the active device regions
122
during operation of the integrated circuit on the IC die
102
. In addition, the power dissipated through such active device regions
122
is dramatically increasing as the clocking speed of integrated circuits, such as for microprocessors for example, is increasing with technological advancement. Thus, for many modem integrated circuits fabricated on the IC die
102
, the front-side
124
of the IC die
102
heats up rapidly, such as in seconds or in less than a second, during operation of the integrated circuit on the IC die
102
.
In addition, such rapid heating of the front-side
124
from operation of the integrated circuit on the IC die
102
is localized to the interface between the front side
124
of the IC die
102
and the underfill material
130
. The underfill material
130
is typically comprised of a material such as epoxy which is not a good heat conductor. The interlevel dielectric material
128
absorbs the heat generated at the active device regions
122
of the front-side
124
of the IC die
102
. Thus, the interface between the front side
124
of the IC die
102
and the underfill material
130
including the interlevel dielectric material
128
heats up rapidly from operation of the integrated circuit on the IC die
102
.
Such rapid heating at the interface between the front side
124
of the IC die
102
and the underfill material
130
including the interlevel dielectric material
128
causes thermal stress at such an interface. For example, with such thermal stress, the underfill material
130
may undesirably delaminate from the IC die
102
such that the IC die
102
is not securely mounted to the IC package. It is desired to assess the effect of such thermal stress from the rapid heating localized at the interface between the front side
124
of the IC die
102
and the underfill material
130
including the interlevel dielectric material
128
from operation of the integrated circuit on the IC die
102
.
However, the prior art mechanism of temperature cycling to the high-end temperature within the heating chamber
110
of
FIG. 2
does not accurately simulate such rapid heating localized at the interface between the front side
124
of the IC die
102
and the underfill material
130
including the interlevel dielectric material
128
from operation of the integrated circuit on the IC die
102
. With the heating chamber
110
of
FIG. 2
in the prior art, the whole IC package
100
is heated inward from the temperature gradient of the heated environmental temperature within the heating chamber
110
. Thus, the heating is not localized to the interface between the front side
124
of the IC die
102
and the underfill material
130
including the interlevel dielectric material
128
. In addition, such heating of the IC package
100
within the heating chamber
110
of
FIG. 2
in the prior art is gradual over a time period of minutes. Thus, heating is not rapid over a time period of seconds or less than a second.
Thus, a temperature cycling mechanism is desired for more accurately simulating the rapid heating localized at the interface between the front side
Cao Lihong
Chin Jiann Min
Mai Zhihong
Choi Monica H.
Trinh Michael
LandOfFree
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