Method and system for stressing semiconductor wafers during...

Details Method and system for stressing semiconductor wafers during... Method and system for stressing semiconductor wafers during...

2007-09-25

2007-09-25

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S760020, C324S763010

Reexamination Certificate

active

11133843

ABSTRACT:
A method and system for testing a plurality of semiconductor dice on a semiconductor wafer during burn-in includes forming a plurality of semiconductor dice with each die including an integrated circuit and built-in self stress circuitry coupled thereto. The built-in self stress circuitry includes contacts coupled thereto that are configured for probing by a probe card on a burn-in tester. The built-in self stress circuitry, through an interface with the integrated circuit, generates signals for exercising the operation of the integrated circuit during burn-in testing. Each of the plurality of semiconductor dice on the semiconductor wafer are individually controllable by the burn-in tester.

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