Method and system for stacking integrated circuits

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S692000, C257S698000, C257S777000, C257SE25013, C438S109000

Reexamination Certificate

active

07863720

ABSTRACT:
A method and system for stacking integrated circuits is described. An integrated circuit stack is formed by stacking integrated circuit pairs. The integrated circuit pairs are formed by connecting an active surface of a first integrated circuit to an active surface of a second integrated circuit using flip chip bonding. The first integrated circuit pair is connected to a substrate using an adhesive. The other integrated circuit pairs are stacked sequentially on the first integrated circuit pair using an adhesive. Wire bonding is used to connect the second integrated circuit in each of the integrated circuit pairs to the substrate.

REFERENCES:
patent: 5229960 (1993-07-01), De Givry
patent: 6469370 (2002-10-01), Kawahara et al.
patent: 6472741 (2002-10-01), Chen
patent: 6511901 (2003-01-01), Lam
patent: 6555917 (2003-04-01), Heo
patent: 6611434 (2003-08-01), Lo
patent: 6621169 (2003-09-01), Kikuma
patent: 6759307 (2004-07-01), Yang
patent: 6900528 (2005-05-01), Mess et al.
patent: 2001/0000013 (2001-03-01), Lin
patent: 2001/0003375 (2001-06-01), Kovats et al.
patent: 2002/0180025 (2002-12-01), Miyata et al.
patent: 2003/0089998 (2003-05-01), Chan et al.
patent: 2004/0021230 (2004-02-01), Tsai et al.
patent: 2005/0173807 (2005-08-01), Zhu et al.
patent: 0782191 (1997-02-01), None
patent: H11-177020 (1999-07-01), None
patent: H11-354563 (1999-12-01), None
patent: 2000-101016 (2000-04-01), None
patent: 2001-29182 (2001-10-01), None
patent: 2003133509 (2003-09-01), None
International Search Report dated Nov. 16, 2005.
Written Opinion of the International Searching Authority dated Nov. 16, 2005.
European Examination Report, from corresponding EP Application No. 05 754 295, mailed Dec. 16, 2009, 3 pages.
Office Action from related JP Application No. 2007-515236, mailed Jul. 20, 2010, including a translation into English, 7 pages.

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