Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-03-21
1998-04-28
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518511, 36518518, 36518529, G11C 1140
Patent
active
057454108
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to floating gate memory devices, such as flash memory, and in particular to methods and circuits for repairing over-erased floating gate memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. Several popular classes of non-volatile memory are based on arrays of floating gate memory transistors which are electrically erasable and programmable.
The act of programming a memory array of floating gate memory transistors in one popular approach involves injecting the floating gate of addressed cells with electrons which causes a negative charge to accumulate in the floating gate and the turn-on threshold of the memory cell to increase. Thus, when programmed, the cells will not turn on, that is, they will remain nonconductive when addressed with read potentials applied to the control gates. The act of erasing a cell having a negatively charged floating gate involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate. For an opposite polarity array, programming involves selectively removing electrons from the addressed cells' floating gates.
Floating gate memory cells suffer the problem of over-erasure. particularly when erasing involves lowering the threshold by removing electrons from the floating gate. During the erase step, over-erasure occurs if too many electrons are removed from the floating gate leaving a slight positive charge. The positive charge biases the memory cell slightly on, so that a small current may leak through the memory even when it is not addressed. A number of over-erased cells along a given data line can cause an accumulation of leakage current sufficient to cause a false reading.
In addition to causing false readings, when floating gate cells are over-erased, it makes it difficult to successfully reprogram the cells using hot electron programming, particularly with embedded algorithms in the integrated circuits. This difficulty arises because the amount of electrons needed to move an over-erased cell to the programmed state is larger than for normal cells.
Further, because the erase and program operations can affect different cells in a single array differently, floating gate memory designs often include circuitry for verifying the success of the erasing and programming steps. See, for instance, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH MEMORY, invented by Jungroth. If the array does not pass erase verify, the entire array is usually re-erased. The re-erase process can aggravate over-erased cells in the array.
One solution to the over-erase problem associated with the erase verification process is disclosed in U.S. Pat. No. 5,414,664, FLASH MEMORY WITH BLOCK ERASE FLAGS FOR OVER-ERASURE PROTECTION, issued to Lin et al. on May 9, 1995, which shows a method and a device where only those blocks which fail the erase verify operation are re-erased. Accordingly, a re-erase of the entire array after each verify operation is not required. This mitigates the over-erase phenomenon, but does not solve it entirely.
Thus, a repair process has been developed to correct over-erased cells. U.S. Pat. No. 5,233,562, entitled METHODS OF REPAIRING FIELD-EFFECT CELLS IN AN ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE MEMORY DEVICE, issued to Ong, et al., describes processes for such repair using so called drain disturb, source disturb or gate disturb techniques. After each repair in the Ong patent, a time consuming repair verification operation of the entire array is provided. See, also, U.S. Pat. No. 5,416,738 to Shrivastava for further background information.
In any case, the repair and repair verification processes are time-consuming. Therefore, a method and device which repairs over-erased cells in FLASH memory, and other floating gate memory, more quickly and efficient
REFERENCES:
patent: 4875188 (1989-10-01), Jungroth
patent: 5233562 (1993-08-01), Ong et al.
patent: 5414664 (1995-05-01), Lin et al.
patent: 5416738 (1995-05-01), Shrivastava
patent: 5424993 (1995-06-01), Lee et al.
patent: 5438544 (1995-08-01), Makino
patent: 5508959 (1996-04-01), Lee et al.
Chang Kuen-Long
Chen Chia-Shing
Chen Hun-Song
Dang-hsing Yiu Tom
Lee I-Long
Ho Hoai V.
Macronix International Co. Ltd.
Nelms David C.
LandOfFree
Method and system for soft programming algorithm does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for soft programming algorithm, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for soft programming algorithm will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1539320