Computer graphics processing and selective visual display system – Computer graphics processing – Graph generating
Reexamination Certificate
1999-09-13
2002-08-20
Brier, Jeffery (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Graph generating
C702S182000, C714S039000
Reexamination Certificate
active
06437783
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
This invention relates generally to system performance and more specifically to measuring and displaying throughputs on multiple busses.
II. Background Information
In a computer system, the bus is used to move information between devices. A bus defines a pathway for signals to flow between devices in the computer. Examples of busses include, among others, the system memory bus, the processor bus, the Accelerated Graphics Port (“AGP” Version 2.0, 1998) (a dedicated high-speed bus directly between the chipset and the graphics controller), and the Peripheral Component Interconnect (“PCI” Version 2.2, 1998) bus (bus attaching a wide variety of input and output devices, such as disk controllers, local area network chips, and video capture systems).
Computer systems also contain a chipset. The chipset controls traffic between multiple busses that need to access the same device. Chipsets also perform the function of figuring out which location is being addressed in either the random access memory (“RAM”) or the read-only memory and then commanding the corresponding chips, single inline memory module, or dual inline memory module to supply the information at that location. Devices such as system memory can only service a certain number of requests at a time, therefore, the chipset schedules and orders requests from multiple busses to ensure that the device is accessed efficiently. The strength of a chipset is measured by how quickly the chipset services requests from multiple busses vying for access to a device such as memory.
Emerging applications that provide arcade-quality graphics, interactive three dimensional (“3D”) reference titles, interactive video, and exhilarating 3D data visualization impose a host of rigorous requirements on the computer system, including more detailed texturing. Texturing allows the creation of lifelike surfaces and shadows within the 3D image. In the past, complex graphics data, such as texture maps which are stored in the system memory, had to travel to the graphics controller over the PCI bus. Thus, as complex graphics data, such as texture maps, have grown in size (a single texture map can be in of 20 MB), the PCI bus became a bottleneck.
The AGP is a new port designed to relieve graphics bottlenecks by adding a new dedicated high-speed interconnect directly between the chipset and the graphics controller. This removes bandwidth-intensive 3D and video traffic from the constraints of the PCI bus. While the PCI bus supports a maximum of 132 MB/s, the AGP at 66 MHZ supports a maximum of 533 MB/s.
In addition new chipsets, such as the Intel® 440BX chipset, have improved throughputs between the central processing unit, the AGP, system memory, and the PCI bus by combining enhanced bus arbitration, deeper buffers, and improved memory control. The new chipsets allow for faster servicing of requests from high throughput devices such as Graphics Controllers utilizing the AGP.
Current techniques for displaying throughputs are cumbersome and difficult to decipher. They generally measure throughputs sequentially, rather than at randomly distributed intervals, and graph these throughput measurements against time. Current techniques do not simultaneously display the throughput on more than one bus. These techniques do not adequately demonstrate that application programs such as 3D graphics and full-motion video require huge amounts of data and thus require devices such as the AGP. In such cases, the AGP can increase the overall throughput by removing 3D and video traffic from the slower PCI bus thus freeing it up. By freeing up the slower PCI bus, the AGP allows high-speed devices attached to the PCI bus to get the devices' requests serviced quicker.
At the present time, there exists no means of directly measuring or visualizing a chipset's ability to manage high volumes of input/output traffic. Those seeking chipset performance information are forced to rely on system level benchmarks, which inadequately showcase high performance chipsets and are dependent on many system parameters other than the performance of the chipset. Existing benchmarks rely on commercially available applications to generate system loads. These benchmarks are too light (i.e., the traffic generated by the benchmark to the chipset is too light) to stress the performance of advanced chipsets and seldom include more than one type of concurrent chipset contention (i.e., may include memory contention but does not also include processor bus contention). Thus, the chipset's concurrent abilities remain largely unused and unmeasured when using a contemporary benchmark test.
Also, existing benchmarks are flawed because they measure the performance of the system as a whole with a large number of external variables, such as video card and disk speed, affecting the results as much or more than the chipset. Thus, the results from a contemporary benchmark typically vary little from one chipset to the next, as chipset performance is only a minor fraction of the overall “score” reported by these programs. This problem increases when current bench marking methods are applied to chipsets with strong concurrent abilities that allow for maximum use of the AGP's efficient data transfer modes.
For these reasons, there is a need to simultaneously and at randomly distributed intervals measure and display the throughputs on one or more busses in order to graphically visualize the load an application presents to a system. There is also a need to simultaneously measure and display the throughputs on one or more busses in order to show a chipset's ability to maintain high throughputs simultaneously to the various system agents (such as the AGP or the PCI bus) under test. In addition, the performance capabilities of a chipset need to be throughly exercised in order to differentiate between weak chipsets and chipsets with advanced concurrent capabilities.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method is disclosed for displaying a density function. That method entails measuring signal sets simultaneously and at randomly distributed intervals on the busses under test, analyzing those signal sets to determine the percent occurrences of the signal sets, and displaying those percent occurrences in a graph.
REFERENCES:
patent: 3588837 (1971-06-01), Rash et al.
patent: 3708657 (1973-01-01), Kelling
patent: 3895343 (1975-07-01), Farr
patent: 4176402 (1979-11-01), Sipple
patent: 4290010 (1981-09-01), Blaess et al.
patent: 4445221 (1984-04-01), Reynolds et al.
patent: 4974598 (1990-12-01), John
patent: 5142673 (1992-08-01), De Angelis et al.
patent: 5282213 (1994-01-01), Leigh et al.
patent: 5581482 (1996-12-01), Wiedenman et al.
patent: 5621664 (1997-04-01), Phaal
patent: 5633801 (1997-05-01), Bottman
patent: 5793976 (1998-08-01), Chen et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5850388 (1998-12-01), Anderson et al.
patent: 5903730 (1999-05-01), Asai et al.
patent: 5913043 (1999-06-01), Carter et al.
patent: 6000044 (1999-12-01), Chrysos et al.
patent: 6016080 (2000-01-01), Zuta et al.
patent: 6182247 (2001-01-01), Herrmann et al.
patent: 6275782 (2001-08-01), Mann
patent: 6298315 (2001-10-01), Li et al.
Bock Anthony S.
Cabot Mason B.
Coulson Rick L.
Hady Frank T.
Brier Jeffery
Yang Ryan
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