Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Computer or peripheral device
Reexamination Certificate
1999-04-08
2003-01-14
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Computer or peripheral device
C703S016000, C703S017000, C703S026000
Reexamination Certificate
active
06507809
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and a system for simulating the performance of a computer system. More particularly, the invention is directed to a method and a system for implementing high-speed performance simulation of a computer system by using, a multiplicity of simulation means on a system such as a multiprocessor system.
There are needs, in recent years, for higher sophistication in designing information processing systems such as super computers and mainframes, and for such a highly sophisticated information processing system, it is necessary to analyze its performance experimentally before the actual machine is fabricated. Generally, the performance of an information processing system is determined on the basis of such factors as the hardware architecture including a pipeline structure within a CPU, the structure of a memory such as a cache and the I/O structure, and the quality of compilers for generating software that are to be executed on the information processing system, and it is increasingly important that the performance of these components be analyzed before the actual machine is fabricated and that the results be fully utilized in developing the information processing system and its compilers in order to assure high performance of the information processing system.
As a means for analyzing the performance of an information processing system, performance simulation technology is available. Performance simulation is designed to determine the time (generally the number of cycles) required for executing a given program, the hit rate of a cache, the load latency of a memory and the like of an information processing system to be simulated by creating a model of hardware architecture of the system to be simulated through software and simulating hardware behaviors activated by the given program on that model.
Performance simulation allows the user to analyze the performance of an information processing system and thus to find out hardware defects of the system before the actual machine is available. Performance simulation also allows the user to evaluate the performance of a compiler and an operating system (OS) for the information processing system, and thus contributes to improving the performance of such software.
In performance simulation, a simulation process proceeds on the basis of a synchronization clock cycle of the system to be simulated, and thus the performance of the simulant is evaluated, e.g., every machine cycle or based on the latency of a hardware event that occurs. At any rate, machine cycle is the unit of time used by major simulation methods.
As an exemplary prior art, JP-A-8-180094 discloses a performance simulation technology as described above. The prior art method simulates CPU and memory behaviors by using analysis of system calls of application programs to be executed on a model and address generators.
SUMMARY OF THE INVENTION
Such conventional performance simulation technology has its limit in the scale of an information processing system that can be handled, and thus finds difficulty handling a recently developed information processing system whose logic model is large due to the system having been large-scaled. Even if capable of handling such an information processing system, the conventional technology imposes another problem that the simulation time is increased.
An object of the present invention is to provide a method, a system and an execution program recording medium for simulating the performance of a simulant by means of synchronization technique of every plurality of cycles (&Dgr;T cycle). When the performance simulation of a large-scaled simulant is executed by dividing the simulant into a plurality of subsystems or partial units, the method, the system and the execution program recording medium allow a simulation process to be performed for the whole part of the simulant every &Dgr;T cycle even if the partial units have a shared resource among them, and thus contribute to reducing the overhead time due to synchronization.
Further, another object of the present invention is to provide a method, a system and an execution program recording medium that allow a plurality of performance simulators responsible for partial units having no shared resource to operate concurrently, and that allow a performance simulation process to be performed at high speed onto a large-scaled simulant especially when the plurality of performance simulators are implemented on a multiprocessor-based computer.
To achieve the above object, one aspect of the present invention provides a performance simulation method for determining the performance of an information processing system by simulating a process to be performed on the information processing system, comprising the steps of: preparing a plurality of performance simulation program means for executing performance simulation processes independently of one another and a synchronization program means for causing the performance simulation program means to conduct the simulation processes at a synchronization timing of a plurality of cycles; dividing the information processing system to be simulated into a plurality of subsystems or partial units and allocating said plurality of performance simulation program means to the plurality of divided subsystems or partial units, respectively; and causing said synchronization program means to instruct said plurality of performance simulation program means to sequentially conduct the simulation processes at the synchronization timing of the plurality of cycles, thereby to complete a simulation process for the whole subsystems or partial units of the information processing system.
To achieve the above object, another aspect of the present invention provides a performance simulation method, comprising the steps of: preparing program means for managing occupation of a shared resource among the divided partial units, and communication program means for allowing the performance simulation program means to communicate the occupation of the shared resource to one another; causing the synchronization program means to ford instruct the performance simulation program means to sequentially conduct the simulation processes; and causing the communication program means to instruct the performance simulation program means to communicate the occupation of the shared resource to one another at the synchronization timing data of a plurality of cycles.
To achieve the above object, still another aspect of the present invention provides a performance simulation method comprising a step of causing the performance simulation program means to conduct the simulation processes in parallel onto those of the partial units having no shared resource.
As a result of the afore-mentioned configuration, the present invention can avoid conflict or collision over the occupation of the shared resource among the plurality of performance simulation program means, thereby allowing the plurality of performance simulation program means to conduct simulation processes onto the partial units having the shared resource at the synchronization timing of &Dgr;T cycle. The &Dgr;T cycle may preferably be 2 to 10 cycles. In addition, the present invention allows parallel simulation to be effected by dividing the simulant into the plurality of partial units and by concurrently operating the performance simulation program means that are respectively responsible for the partial units having no shared resource, and thus the simulation processes can be performed at high speed.
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Dirkx et al., Evaluation of simulation strategies for computer networks on Parallel MIMD computers IEEE International conference on computer systems and
Tamaki Yoshiko
Watanabe Isao
Yoshino Taisei
Antonelli Terry Stout & Kraus LLP
Broda Samuel
Hitachi , Ltd.
Thangavelu Kandasamy
LandOfFree
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