Method and system for simulating an operation of a memory

Details Method and system for simulating an operation of a memory Method and system for simulating an operation of a memory

2000-09-11

2004-11-16

Knight, Anthony (Department: 2121)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S021000, C703S024000, C714S033000, C714S041000, C714S718000, C714S741000, C714S819000, C711S144000

Reexamination Certificate

active

06820047

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-315884, filed Nov. 5, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a method and a system for simulating an operation of a memory and, more specifically, to a method and a system which are so improved that an error operation of a memory can be simulated.
As hardware to be designed, such as an LSI, increases in size, a design technique of describing functional specifications of the hardware by computer programs such as hardware description language and simulating an operation of the hardware, has recently been established. The simulation technique using such software allows the operation of a development-targeted LSI to be verified with efficiency.
In order to verify the operation of an LSI having a memory control function, an external memory model describing the operation of a memory to be controlled should be prepared in addition to a functional model of the LSI. The external memory model is generally based on a memory capable of correctly reading out the write data. This is because in most normal semiconductor memory devices such as at DRAM and a SRAM, no errors occur in the read/write operation and the write data can correctly be read out. The operation of the, LSI can thus be verified correctly, provided that an external memory model which reads out write data has only to be prepared.
However, semiconductor memory devices, which is not always able to correctly read out write data like a flash memory (flash EEPROM), have recently started to increase and accordingly a system having a function of detecting a memory error need to be developed. For example, in a memory system using a flash memory, an ECC (error correcting code) is generated in units of write data and stored in a flash memory together with write data and, when data is read out, a memory controller detects and corrects an error of the read data in accordance with the ECC.
To correctly verify the operation of the memory controller, a new external memory model having an error generating function should be prepared.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method and a system capable of easily simulating an error operation of a memory.
Another object of the present invention is to provide a method and a system which are the most suitable for verifying an operation of a memory system using a nonvolatile semiconductor memory such as a flash memory.
In order to resolve the above objects, the present invention is provided with a method of simulating an operation of a memory, comprising the steps of simulating a read/write operation corresponding to a location specified by a first bit set of a memory address including a plurality of bits, using a memory model describing the operation of the memory, and generating an error in the read/write operation of the memory model in accordance with a value of a second bit set of the memory address by making a change to one of write data to be written to the memory model and read data read therefrom, the second bit set being not used for the simulation of the read/write operation using the memory model.
The above simulation method includes an error generating step in addition to a memory operation simulating step. An error can easily be generated in a read/write operation of a memory model only by setting a memory address. A second bit set, which is not used for the simulation of a memory operation, is used as a memory address for indicating the error generation. It is thus unnecessary to prepare a new description of a signal line exclusively for indication of error generation and it is possible to simulate a memory operation containing an error only by the normal descriptions of an address, data, and the like. An error of a memory operation is generated by making a change, such as bit reverse, to write data to be written to the memory model or read data read therefrom. It is thus unnecessary to make a change to a normal memory model itself which correctly reads out write data, and it is possible to simulate an error operation of a memory only by adding a functional description such as bit reversal of write data/read data to the memory model.
It is preferable to define a set of bits for specifying an error generating address and another set of bits for specifying error mode in the second bit set which is not used for the simulation of the memory operation. The error generating step allows an error to be generated in an address position in accordance with a value of the second bit set of the memory address.
When the memory model describes an operation of a nonvolatile semiconductor memory to which write data and an error correction code thereof are written in units of data size, it is preferable to further comprise a step of simulating an error correcting operation of a memory controller for controlling the nonvolatile semiconductor memory, based on the read data read from the memory model and the error correction code, using an LSI model describing an operation of the memory controller. It is thus possible to verify an error correcting operation of the memory controller for controlling a nonvolatile semiconductor memory such as a flash memory.
When an error correcting operation of the memory controller is simulated, it can be verified from various angles by selectively using a first error mode in which data is changed within the number of error correctable bits by an error correction code and a second error mode in which data is changed by the number of bits exceeding the number of error correctable bits by the error correction code.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 4354225 (1982-10-01), Frieder et al.
patent: 4617660 (1986-10-01), Sakamoto
patent: 4800563 (1989-01-01), Itagaki et al.
patent: 5337317 (1994-08-01), Takamisawa et al.
patent: 5671352 (1997-09-01), Subrahmaniam et al.
patent: 5875195 (1999-02-01), Dixon
patent: 6012157 (2000-01-01), Lu
patent: 6053948 (2000-04-01), Vaidyanathan et al.
patent: 6144930 (2000-11-01), Kinzelman
patent: 6539503 (2003-03-01), Walker
patent: 56011700 (1981-02-01), None
patent: 57066597 (1982-04-01), None
patent: 6-162131 (1994-06-01), None
patent: 6-90713 (1994-11-01), None

Affiliated with

Also associated with

Rating

Method and system for simulating an operation of a memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for simulating an operation of a memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for simulating an operation of a memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3355382