Method and system for selective serialization of instruction pro

Details Method and system for selective serialization of instruction pro Method and system for selective serialization of instruction pro

1996-08-12

1998-06-09

Treat, William M.

395392, 395566, 395570, G06F 930, G06F 9312

Patent

active

057649421

ABSTRACT:
The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.

REFERENCES:
patent: 5471593 (1995-11-01), Branigin
Dwyer III, Harry, A Multiple, Out-of-Order, Instruction Issuing System for Superscalar Processors, Cornell University, Aug. 1991.

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