Method and system for sampling a signal

Details Method and system for sampling a signal Method and system for sampling a signal

2007-04-24

2007-04-24

Nguyen, Khai M. (Department: 2819)

Coded data generation or conversion

Sample and hold

C341S155000, C375S355000

Reexamination Certificate

active

11094613

ABSTRACT:
A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.

REFERENCES:
patent: 4188583 (1980-02-01), McCurdy
patent: 4384361 (1983-05-01), Masaki
patent: 4602243 (1986-07-01), Von Bargen et al.
patent: 4694244 (1987-09-01), Whiteside et al.
patent: 4768017 (1988-08-01), Gordon
patent: 4805165 (1989-02-01), Kawamura et al.
patent: 4870699 (1989-09-01), Garner et al.
patent: 4879758 (1989-11-01), DeLuca et al.
patent: 4930126 (1990-05-01), Kazecki et al.
patent: 4996639 (1991-02-01), Ishimoto et al.
patent: 5031233 (1991-07-01), Ragan
patent: 5058203 (1991-10-01), Inagami
patent: 5142699 (1992-08-01), Sato et al.
patent: 5150361 (1992-09-01), Wieczorek et al.
patent: 5151769 (1992-09-01), Immorlica, Jr. et al.
patent: 5241541 (1993-08-01), Farrell et al.
patent: 5280644 (1994-01-01), Vannatta et al.
patent: 5307066 (1994-04-01), Kobayashi et al.
patent: 5355524 (1994-10-01), Higgins, Jr.
patent: 5404547 (1995-04-01), Diamantstein
patent: 5448755 (1995-09-01), Tanaka
patent: 5471471 (1995-11-01), Freeburg et al.
patent: 5471663 (1995-11-01), Davis
patent: 5475684 (1995-12-01), Shimizu
patent: 5519711 (1996-05-01), Sointula
patent: 5586149 (1996-12-01), Connell et al.
patent: 5604928 (1997-02-01), Hamano et al.
patent: 5630224 (1997-05-01), Swail
patent: 5649160 (1997-07-01), Corry et al.
patent: 5731728 (1998-03-01), Greiss
patent: 5758278 (1998-05-01), Lansdowne
patent: 5764693 (1998-06-01), Taylor et al.
patent: 5812936 (1998-09-01), DeMont
patent: 5838741 (1998-11-01), Callaway, Jr. et al.
patent: 5841814 (1998-11-01), Cupo
patent: 5842037 (1998-11-01), Haartsen
patent: 5872540 (1999-02-01), Casabona et al.
patent: 5875449 (1999-02-01), Ono
patent: 5917854 (1999-06-01), Taylor et al.
patent: 5920592 (1999-07-01), Tanaka et al.
patent: 5923761 (1999-07-01), Lodenius
patent: 5953640 (1999-09-01), Meador et al.
patent: 5963604 (1999-10-01), Greiss
patent: 5963885 (1999-10-01), Macq
patent: 6020614 (2000-02-01), Worley
patent: 6166595 (2000-12-01), Moldsvar et al.
patent: 6243597 (2001-06-01), Daanen
patent: 6246335 (2001-06-01), Tsunoda
patent: 6252441 (2001-06-01), Lee et al.
patent: 6300889 (2001-10-01), Piasecki
patent: 6310570 (2001-10-01), Rumreich
patent: 6366622 (2002-04-01), Brown et al.
patent: 6420989 (2002-07-01), Herbold
patent: 6480553 (2002-11-01), Ho et al.
patent: 6498819 (2002-12-01), Martin
patent: 6510185 (2003-01-01), Lee et al.
patent: 6737904 (2004-05-01), Butaud et al.
patent: 6963626 (2005-11-01), Shaeffer et al.
patent: 7046183 (2006-05-01), Bilinskis et al.
patent: 2002/0080728 (2002-06-01), Sugar et al.
patent: 2003/0020521 (2003-01-01), Lee et al.
patent: 2003/0160714 (2003-08-01), Yoshinaga
patent: 2006/0045224 (2006-03-01), Cranford et al.
patent: 0447302 (1991-09-01), None
patent: 0447302 (1991-09-01), None
patent: 00463621 (2000-01-01), None
patent: 00463621 (2000-01-01), None
patent: 1 058 387 (2000-12-01), None
Mehta, Jesal L., “Transceiver architectures for wireless ICs,” RF Designs, www.rfdesign.com, Feb. 2001, pp. 76-96.
Johnston, Jerome, “Switched-Capacitor A/D Converter Input Structures,” Crystal Semiconductor Corp., htt://www.crystal.com, Jan. 1995, pp. 1-6.
U.S. Appl. No. 10/426,042, filed Apr. 29, 2003, Sooch et al.
Foreign Search Report and Written Opinion PCT/US2006/011698, mailed Jul. 27, 2006.
International Search Report & Written Opinion; PCT/US2006/011698; Mailed Jul. 27, 2006.

Affiliated with

Also associated with

Rating

Method and system for sampling a signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for sampling a signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for sampling a signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3756762