Method and system for routing of integrated circuit design

Details Method and system for routing of integrated circuit design Method and system for routing of integrated circuit design

2011-06-21

2011-06-21

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S126000, C716S130000

Reexamination Certificate

active

07966597

ABSTRACT:
The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis for a given routed placement of cells containing said electric circuits on a chip; defining a critical area on said chip based on congestion information; analyzing actual wiring quality within said critical area; comparing an actual wiring quality of said critical area with a reference wiring quality of said critical area; and rerouting said critical area based on a comparison between the actual wiring quality and the reference wiring quality.

REFERENCES:
patent: 5629860 (1997-05-01), Jones et al.
patent: 6598206 (2003-07-01), Darden et al.
patent: 7076758 (2006-07-01), Srinivasan et al.
patent: 2005/0108444 (2005-05-01), Flauaus et al.

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