Method and system for reordering instructions after dispatch in

Details Method and system for reordering instructions after dispatch in Method and system for reordering instructions after dispatch in

1995-07-27

2000-03-21

Maung, Zami

395393, 39580023, G06F 900

Patent

active

060411678

ABSTRACT:
A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.

REFERENCES:
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4620292 (1986-10-01), Hagiwara et al.
patent: 4796218 (1989-01-01), Tanaka et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5060148 (1991-10-01), Isobe et al.
patent: 5075840 (1991-12-01), Grohoski et al.
patent: 5075846 (1991-12-01), Reininger et al.
patent: 5077692 (1991-12-01), McMinn
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5177701 (1993-01-01), Iwasa
patent: 5185871 (1993-02-01), Frey et al.
patent: 5197135 (1993-03-01), Eickemeyer et al.
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5210861 (1993-05-01), Shimoda
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5222229 (1993-06-01), Fukuda et al.
patent: 5222244 (1993-06-01), Carbine et al.
patent: 5257214 (1993-10-01), Mason et al.
patent: 5257216 (1993-10-01), Sweedler
patent: 5257354 (1993-10-01), Comfort et al.
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5268855 (1993-12-01), Mason et al.
patent: 5269017 (1993-12-01), Hayden et al.
patent: 5274818 (1993-12-01), Vasilevsky et al.
patent: 5297267 (1994-03-01), Inoue
patent: 5307483 (1994-04-01), Knipfer et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5495590 (1996-02-01), Comfort et al.
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5613080 (1997-03-01), Ray et al.
patent: 5627983 (1997-05-01), Popescu et al.
The Metaflow architecture by Popescu et al., 1991 IEEE publication, pp. 10-13, 63-73.
The architecture of pipelined computers by Kogge, 1981, pp. 268-271.
IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990, "Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers" to G. S. Sohi, pp. 349-359.

Affiliated with

Also associated with

Rating

Method and system for reordering instructions after dispatch in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for reordering instructions after dispatch in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for reordering instructions after dispatch in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-736856