Method and system for removing hardware design overlap

Boots – shoes – and leggings

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G06F 1750

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active

059432438

ABSTRACT:
Disclosed is a method and system for removing hardware overlap for use with a computer aided design apparatus. The method and system remove overlap by separately classifying all free blocks and blocks fixed in place, and then shifting cells between free blocks while maintaining the same relative ordering of the cells. Thus, all move bounds are respected and only cells that exist in free blocks actually move. The operation takes place one partition at a time, whereby a typical partition includes a row of cells.

REFERENCES:
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5309371 (1994-05-01), Shikata et al.
patent: 5398195 (1995-03-01), Kim
patent: 5406498 (1995-04-01), Yabe
patent: 5410491 (1995-04-01), Minami
patent: 5493510 (1996-02-01), Shikata
patent: 5535134 (1996-07-01), Cohn et al.
patent: 5619419 (1997-04-01), D'Haeseleer et al.
patent: 5638288 (1997-06-01), Deeley
patent: 5699265 (1997-12-01), Scepanovic et al.
patent: 5808899 (1998-09-01), Scepanovic et al.
patent: 5812740 (1998-09-01), Scepanovic et al.
Choi et al. ("A floorplanning algorithm using rectangular Voronoi diagram and force-directed block shaping", IEEE Comput. Soc. Press, 1991 IEEE International Conference on Computer-Aided Design, Nov. 11, 1991, pp. 56-59).
Dong et al. ("Constrained floorplan design for flexible blocks", IEEE Comput. Soc. Press, 1989 IEEE International Conference on Computer-Aided Design, Nov. 5, 1989, pp. 488-491).
Ohmura et al. ("Overlap resolution problem for block placement in VLSI layout", Electronics and Communiations in Japan, Part 3 (Fundamental Electronic Science), vol. 73, No. 6, pp. 68-77, Jun. 1, 1990).
Yamada et al. ("A block placement mehtod based on balloon model", IEEE International Symposium on Circuits and Systems, vol. 3, May 1, 1990, pp. 1680-1683).
Ying et al. ("An analytical approach to floorplanning for hierarchical building blocks layout (VLSI)", IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, No. 4, pp. 403-412, Apr. 1989).

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