Method and system for register allocation using multiple interfe

Details Method and system for register allocation using multiple interfe Method and system for register allocation using multiple interfe

1996-03-25

1999-05-04

Voeltz, Emanuel Todd

G06F 945

Patent

active

059013176

ABSTRACT:
Allocation of real registers to virtual or symbolic registers represented by nodes in an interference graph is performed with a compiler using a primary interference graph and a secondary interference graph. The primary interference graph contains the standard edges indicating latency between virtual registers represented by nodes linked by the edges. Secondary links between nodes indicate conditional conflicts which can be tolerated but which, if avoided in the register allocation process, improve the execution speed of program segments. The conditional conflict specifically referenced is the requirement for paired register designation in single precision floating point operations in which registers are identified as pairs, rather than as individual registers.

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