Static information storage and retrieval – Powering
Reexamination Certificate
1999-09-30
2001-05-08
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Powering
C365S233100, C365S189050, C365S154000
Reexamination Certificate
active
06229750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is an improved system and method for reducing power dissipation in a semiconductor device by controlling the operation of the device through the use of an improved clock splitting arrangement. More particularly, the present invention uses an improved clock splitting circuit and logic to provide a better turnoff arrangement for a semiconductor storage device such as a master/slave latch where the turn off is accomplished earlier in the cycle which reduces power consumption and allows for a later turn off through the use of an early and late control signals based on early and late enable signals and logic to combine the control signals.
2. Background Art
As semiconductor devices get larger with more components fabricated on a single chip, it becomes important to reduce the power consumed and the heat generated by the chip. The power consumed in a factor of several different variables, including particularly the number of times that a semiconductor changes states. It would be therefore be desirable to turn off the semiconductor elements which are not being used, and turn them off as early as possible, while allowing for a decision that the semiconductor storage may not be needed still to be determined later in the cycle without losing the opportunity to turn off the semiconductor storage during that cycle.
Several systems for controlling power consumption in a semiconductor storage through the use of a clock splitter have been proposed. One of these involved the use of a slit clock to turn the storage device off to reduce the power consumed. Another system involved the use of wait states (or a lost cycle) when the devices were shut down (to avoid losing data). Still another approach slows down the clock (elongating the clocking signal) to allow for reduced power consumption in the semiconductor storage.
However, the prior art devices have the disadvantages that more power than necessary was still consumed by the semiconductor storage device, since the device was on and changing states more than necessary. Either the latch device was not turned off as early as possible to avoid consuming power or it was not turned off when it could have been turned off.
Further, in some systems, an additional cycle (a so-called “wait state”) was required when the latches are turned on (or turned off), reducing performance of the system and the latches. Also, when the clock signal is elongated and therefore slowed down, the performance of the system (in cycles per unit of time) is undesirably reduced.
Accordingly, the prior art latch control circuits consumed more power than was necessary and could have been turned off without adverse effect on the logic.
Other disadvantages and limitations of the prior art systems will be apparent to those skilled in the art to which the invention applies in view of the following description of the preferred embodiment of the present invention, taken together with the accompanying drawings and the appended claims.
SUMMARY OF THE INVENTION
The present invention overcomes the limitations and disadvantages of the prior art systems by providing an improved semiconductor storage device which consumes less power while operating to allow full functions at full speed (without unnecessary “wait states” and without slowing the clock).
The present invention has the advantage that it is simple and easy to fabricate and does not require substantial additional cost, hardware or design effort.
The present invention has the additional advantage that it is fast and provides for a shut down of the semiconductor storage device when it is not needed, yet renders the storage device fully operational when data for processing in the semiconductor storage device is present.
The system for controlling the operation of the semiconductor storage devices in the present invention also has the benefit that it does not require additional cycles (or wait states) to effect turnoff or to recover from a turnoff. The system of the present invention also does not require that the clock be slowed down (e.g., through use of elongated cycles), with the attendant reduction in performance.
The present system also allows for an extended period during which the decision can be made to turn off the logic of a semiconductor latch without losing the opportunity to turn off the logic during a particular cycle, while the clock is at the rated maximum frequency. The use of an earlier early enable signal and a later early enable signal allows making a decision to turn off the relevant logic early in the cycle, while still allowing a later decision to be made to turn off the logic.
The present invention allows a determination to be made at several different times during the cycle that a semiconductor storage will not be needed during that cycle and to turn off the logic and generation of clock signals. If it is known immediately at the beginning of the cycle that the memory will not be needed, an early clocking signal is suppressed and a late clocking signal is not generated and a large amount of the power that the semiconductor memory and the associated clock splitting circuitry would otherwise consume would be saved. If it is determined later in the cycle that the semiconductor memory will not be needed during the cycle (before the middle of the cycle), the early clocking signal can still be suppressed, with a lesser, but still significant saving in power consumption. Finally, if it is determined late in the cycle that the semiconductor memory will not be needed, then a late enable (or disable) signal is generated to turn off part of the semiconductor memory and save some of the power which would otherwise be consumed in the semiconductor memory and associated clock splitting circuitry, an amount of savings which is less than is saved if the semiconductor memory were shut down earlier.
Other objects advantages of the present invention will be apparent to those skilled in the relevant art in view of the following description of the preferred embodiment, taken together with the accompanying drawings and the appended claims.
REFERENCES:
patent: 4912709 (1990-03-01), Teske et al.
patent: 5072132 (1991-12-01), Samaras et al.
patent: 5455931 (1995-10-01), Camporese et al.
patent: 5719878 (1998-02-01), Yu et al.
patent: 5789957 (1998-08-01), Fucili et al.
patent: 6061289 (2000-05-01), Itoh et al.
Correale, Jr. Anthony
Lynch Robert James
Flynn John D.
Hoang Huan
International Business Machines - Corporation
McConnell Daniel E.
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